臺灣博碩士論文加值系統

隨著物聯網的應用越來越普及，受限的電池容量限制了這些嵌入式系統的使用，而考慮節能以延長電池供電設備的壽命時，動態電源管理技術可以打開和關閉設備的某些部分，以減少當前未使用時的耗能，但是如果DRAM用作主記憶體並且已經關閉，則系統需要加載並初始化一些數據並將數據重新發送回DRAM，以便在系統準備好運作之前恢復先前狀態的主記憶體的資料內容，而其造成的恢復延遲可能太長，這可能導致違反系統的效能需求。著眼於此一現象並且進一步考慮非揮發性記憶體的應用時，部分資料將可保留在非揮發性記憶體中，在執行時期直接存取，以之減少載入與寫回的時間，讓動態電源管理技術的相關技術更加實務可行。而除了節省恢復時間之外，系統運行時期的性能仍然是一個關鍵的問題。因此，本論文將分析資料的性質與記憶體之特性，妥善地配置與搬移資料，進而在符合效能需求的前提下，增加系統可用動態電源管理技術省電的閒置時間，得到省電結果與延長非揮發性記憶體的使用壽命。

As applications of Internet of things and wearable devices are more and more popular, the restricted battery capacity still limit the usage of these advanced embedded systems. When energy saving is considered to extend the lifetime of battery-powered devices, the Dynamic Power Management (DPM) technique can switch on and off some parts of a device to reduce energy consumption when they are not currently used. If DRAM modules are used as main memory and have been switched off, the system needs to load and initialize some data and binary back to DRAM for resuming the previous state of main memory before the system is ready for its services. The resuming latency might be too long, in which the performance constraint of the system might be violated. While Non-Volatile Memory (NVM), e.g., phase change memory and spin torque transfer RAM, is going to mature, this work rethinks the management of memory and storage with NVM for eliminating the resuming latency, and thus, the DPM energy saving can be more practical and useful. In addition to the resuming time saving, the run-time performance of a system is still a critical design issue. Thus, some data and binary movement among various types of memory is conducted by our solution to meet the performance requirements while the energy consumption is reduced by extending the system dormant time with shorter resuming latency.

Contents
Recommendation Letter from the Thesis Advisor
Thesis Oral Defense Committee Certification
Acknowledgements iii
Chinese Abstract iv
Abstract v
1 Introduction 1
2 Literature Study 3
3 System Architecture and Problem Definition 5
3.1 System Architecture . . . . . . . . . . . . . . . . . . . . 5
3.2 Problem Definition . . . . . . . . . . . . . . . . . . . . 7
4 Data Allocation with Heterogeneous Nonvolatile Memory 9
4.1 Allocation Algorithm for Minimizing Busy Time . . . . 9
4.2 Implement Remarkes for NVM Protection . . . . . . . . 14
5 Performance Evaluation 16
5.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . 16
5.2 Experimental Results . . . . . . . . . . . . . . . . . . . 18
6 Conclusion 24
Reference 25


List of Figures
3.1 System Architecture . . . . . . . . . . . . . . . . . . . . 6
4.1 Algorithm Work Flow . . . . . . . . . . . . . . . . . . . 10
5.1 Energy consumption of all methods with different access
sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 Busy time of all methods with different access sizes . . . 19
5.3 PCM write of all methods with different access sizes . . 20
5.4 Energy consumption of all methods with different data
workload . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.5 Energy consumption of all methods with different write
ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
List of Tables


4.1 Operating Time Cost . . . . . . . . . . . . . . . . . . . 11
4.2 Notation Description . . . . . . . . . . . . . . . . . . . 12
5.1 Parameter Setting . . . . . . . . . . . . . . . . . . . . . 17

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