臺灣博碩士論文加值系統

在本文中提出了對固定寬度二進制改良布斯乘法器（FWBM）之精確度的微調精確度的方法。我們利用智能進化算法（IEA）來決定最適合的補償電路，與傳統微調機制較不一樣的地方在於，本文藉由逐位元的微調方式來取代傳統逐行的粗調方式。此外，基於底部符號位元（BSB）設計最適合的補償值，讓補償後的值能夠接近最佳解。通過本文提出微調FWBM精確度的方法，藉由較有效率的找尋最佳解的方式－正交實驗設計，來避免龐大的模擬時間。根據本文所提出的系統化且有效率的方法之電路架構，達到低誤差和低硬體面積消耗的多目標最佳化設計。本文通過訊號雜訊比（SNR）與硬體面積的比例來驗證基於本文方法的電路架構之表現。基於TSMC 0.18-μm合成的硬體表現與基於MATLAB運算誤差的實驗結果，相較於其他先前的工作，本文提出的方法可以達到在低硬體成本下改善固定寬度乘法器的精確度。

In this thesis, fine-tuning the accuracy of the fixed-width two’s complement modified Booth multiplier (FWBM) is proposed. Instead of conventional column-wise compensation techniques, we utilize intelligent evolution algorithm (IEA) to determine the most suitable compensated circuit for element-wise FWBM. In addition, the adaptive compensation value based on bottom sign bit (BSB) is designed for each nearly optimized FWBM. In this way, the hardware area and the accuracy can be optimized without the exhaustive simulation, but with the efficient searching method of orthogonal experimental design. The proposed circuits achieve low error and low hardware cost by this systematic and efficient method. In this thesis, the performance is validated by the merit of signal noise ratio (SNR) divided by the hardware area. The experimental results of SNR calculated by Matlab and area synthesized by Cadence SoC Encounter with TSMC 0.18-μm standard cell library show that the proposed compensation circuits can improve the performance of the merit.

目 錄
指導教授推薦書
口試委員會審定書
致謝 iii
摘要 iv
Abstract v
目 錄 vi
圖目錄 viii
表目錄 ix
第 1 章 介紹 - 1 -
1-1 固定寬度乘法器 - 1 -
1-2 文獻回顧 - 2 -
1-3 各種PEB的優勢和限制 - 3 -
第2章 前言 - 6 -
2-1 布斯改良式乘法器 - 6 -
2-2 布斯改良式固定寬度乘法器 - 7 -
2-3 最底部符號位元和輔助位元對精確度的影響 - 11 -
2-4 智能演化式演算法 - 15 -
2-4-1 演化式演算法 - 15 -
2-4-2 正交實驗設計 - 18 -
2-4-3 正交表(Orthogonal Array) - 19 -
第3章 實驗設計 - 22 -
3-1 實驗架構 - 22 -
3-2 實驗流程 - 23 -
3-2-1 設計正交表 - 24 -
3-2-2 計算誤差值和補償值 - 26 -
3-2-3 因子分析與微調機制 - 31 -
第4章 結果與討論 - 35 -
4-1 研究結果與討論 - 35 -
4-2 固定寬度乘法器比較與討論 - 39 -
4-3 未來展望與討論 - 42 -
第5章 結論 - 45 -
參考文獻 - 47 -

圖目錄
圖 2-2-1 輸入為8位元的固定寬度乘法器部分乘積 - 8 -
圖 2-2-2 輸入為8位元且h=1之截斷部分每個低有效位元的期望值 - 10 -
圖 2-3-1 輸入為8位元且最底部符號位元為1和0時，TPcal中每個位元的期望值 - 13 -
圖 2-4-1-1 演化式演算法共同運作流程 - 16 -
圖 2-4-2-1 三個因素、兩個水平的部分因子 - 18 -
圖 3-2-2-1 輸入寬度10位元之A、B、C權重位置 - 31 -
圖 4-1-1輸入寬度為8位元之補償電路 - 36 -
圖 4-3-1 基於Li et al.[13]精神的硬體實現 - 44 -
圖 4-3-2 輸入寬度8位元且h=2和BSB為0的截斷部分中低有效位元期望值的估算，而估算方式是基於Li et al.[13]的精神 - 44 -

表目錄
表 2-1-1布斯演算法編碼 - 7 -
表 2-2-1 頂部符號位元和其它符號位元布斯編碼的機率比較 - 11 -
表 2-2-2 輸入為8位元的部份乘積 - 11 -
表 2-4-3-1 正交表L4(34)之四因子三水平 - 20 -
表 3-2-1-1 輸入寬度為8位元且截斷部分為一行高顯著位元的正交表 - 25 -
表 3-2-1-2 輸入寬度為10位元且截斷部分為一行高顯著位元的正交表 - 25 -
表 3-2-1-3輸入寬度為12位元且截斷部分為一行高顯著位元的正交表 - 26 -
表 4-1-1 輸入寬度8位元之因子分析 - 37 -
表 4-1-2 輸入寬度10位元之因子分析 - 37 -
表 4-1-3 輸入寬度12位元之因子分析 - 38 -
表 4-1-4 不同輸入寬度下最底部符號位元為0和1的補償值 - 38 -
表 4-2-1 本文機制與以前文獻訊號雜訊比的比較 - 40 -
表 4-2-2　本文機制與以前文獻硬體面積的比較 - 41 -
表 4-2-3 本文機制與GPEB 的SNR/AREA比較 - 42 -

參考文獻
[1] S. R. Kuang, J. P. Wang, C. Y. Guo, "Modified Booth multipliers with a regular partial product array", IEEE Trans. Circuits Syst. II Exp. Briefs, vol. 56, no. 5, pp. 404-408, May 2009.

[2] M. A. Song, L. D. Van, S. Y. Kuo, "Adaptive low-error fixed- width Booth multipliers", IEICE Trans. Fundam., vol. E90-A, no. 6, pp. 1180-1187, Jun. 2007.

[3] Y. H. Chen, T. Y. Chang, R. Y. Jou, "A statistical error-compensated Booth multiplier and its DCT applications", Proc. IEEE Region 10 Conf., pp. 1146-1149, 2010.

[4] S. J. Jou, M. H. Tsai, Y. L. Tsao, "Low-error reduced-width Booth multipliers for DSP applications", IEEE Trans. Circuits Syst. I Fundam. Theory Appl., vol. 50, no. 11, pp. 1470-1474, Nov. 2003.

[5] J. P. Wang, S. R. Kuang, S. C. Liang, "High-accuracy fixed-width modified Booth multipliers for lossy applications", IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 1, pp. 52-60, Jan. 2011.

[6] T. B. Juang, S. F. Hsiao, "Low-error carry-free fixed-width multipliers with low-cost compensation circuits", IEEE Trans. Circuits Syst. II Exp. Briefs, vol. 52, no. 6, pp. 299-303, Jun. 2005.

[7] Y. H. Chen, C. Y. Li, T. Y. Chang, "Area-effective and power-efficient fixed-width Booth multipliers using generalized probabilistic estimation bias", IEEE J. Emerging Sel. Topics Circuits Syst., vol. 1, no. 3, pp. 277-288, Sep. 2011.

[8] Y. H. Chen, T. Y. Chang, "A high-accuracy adaptive conditional-probability estimator for fixed-width Booth multipliers", IEEE Trans. Circuits Syst. I Reg. Papers, vol. 59, no. 3, pp. 594-603, Mar. 2012.

[9] C. Y. Li, Y. H. Chen, T. Y. Chang, J. N. Chen, "A probabilistic estimation bias circuit for fixed-width Booth multiplier and its DCT applications", IEEE Trans. Circuits Syst. II Exp. Briefs, vol. 58, no. 4, pp. 215-219, Apr. 2011.

[10] Y. H. Chen, "An accuracy-adjustment fixed-width Booth multiplier based on multilevel conditional probability", IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 1, pp. 203-207, Jan. 2015.

[11] Y. H. Chen, C. Y. Li, L. A. Lai, “Fine-Tuning Accuracy Using Conditional Probability of the Bottom Sign-Bit in Fixed-Width Modified Booth Multiplier”, Circuits Syst Signal Process 37:3115–3130, 2018

[12] S. Y. Ho, L. S. Shu, J. H. Chen, “Intelligent Evolutionary Algorithms for Large Parameter Optimization Problems”, IEEE Transactions on Evolutionary Computation, vol. 8, no. 6, December 2004

[13] B. K. Mohanty, V. Tiwari, “Modified PEB Formulation for Hardware-Efficient Fixed-Width Booth Multiplier”, Circuits, Systems, and Signal Processing Volume 33, Issue 12, pp 3981–3994

[14] C. Y. Li, Y. H. Chen, L. A. Lai, “Simple and Hardware-efficient Row-based Direct-Mapping estimators in Fixed-width Modified Booth Multipliers”

[15] W. Q. He, Y. H. Chen, and S. J. Jou, “Dynamic Error-compensated Fixed-width Booth Multiplier Based on Conditional-Probability of Input Series,” Circuit Syst. Signal Process, vol. 35, no. 8, pp. 2972-2991, Aug. 2016.

[16] W. Q. He, C. Y. Liu, and Y. H. Chen, “A high accuracy fixed-width Booth multiplier using select probability estimation bias,” 2014 4th IEEE International Conference on Information Science and Technology., pp. 385-388, 2014.

[17] C. H. Chen Signal processing handbook. CRC Press. 1988: 234. ISBN 9780824779566.

[18] C. Y. Li, Y. H. Chen, L. A. Lai, “Row-based Direct-Mapping Estimators in Fixed-width Modified Booth Multipliers”