臺灣博碩士論文加值系統

由於現今的卷積神經網路(Convolutional Neural Network,CNN)裡，超過90%的運算來自卷積(Convolution)，故在卷積(Convolution)的硬體加速器的實現上其效率和性能，將影響整個CNN在inference時的執行速度。
在Convolution裡包含了四種迴圈的乘法累加運算，在實現硬體時會產生設計出的電路面積過大，使得成本過高。而在先前的技術中採用有限的循環優化技術，例如Loop unrolling，Loop Tiling和Loop interchange，僅在加速器架構和數據流的一些調整。而該技術通過重新配置架構來優化整個系統的效率，包括加速器晶片和DRAM，用於各種CNN的使用。 CNN在現代人工智慧系統中得到了廣泛的應用，但是也給底層硬體帶來了吞吐量和能源效率方面的挑戰。這是因為它的計算需要使用到大量的數據，而從On-chip和Off-chip創建重要的數據移動，這比計算更耗能。因此，將不同的CNN的數據移動成本最小化是高吞吐量和高能效的關鍵。
而本文將研究如何優化卷積運算的數據移動，將實現出可以有效地的硬體加速方案，並有效地管理數據流(Data Flow)，因為若沒有在硬體設計前完成對Convolution數據流的優化，最終的硬體加速器會很難有效的利用數據並管理移動據，而所提出的CNN加速方案和架構將通過實施LeNet來進行的End to End 的推斷來進行演示，同時最佳化Data Reuse以此來提高性能。對於此架構CNN的整體吞吐量分別在7.4 GOPS。

Since today's Convolutional Neural Network (CNN), more than 90% of operations come from Convolution, its efficiency and performance in the implementation of Convolution's hardware accelerators will affect execution speed of the entire CNN in inference.
In Convolution, four loop multiply-accumulate operations are included. When the hardware is implemented, the designed circuit area is too large, which makes the cost too high. In the Previous Works, limited loop optimization techniques such as Loop unrolling, Loop Tiling and Loop Interchange were used, only some adjustments were made to the accelerator architecture and data flow. The technology optimizes the efficiency of the entire system by reconfiguring the architecture, including accelerator chips and DRAM, for use with various CNNs. CNN has been widely used in modern artificial intelligence systems, but it also brings challenges in throughput and energy efficiency to the underlying hardware. This is because its calculations require the use of large amounts of data, while creating important data movements from On-chip and Off-chip, which is more energy intensive than calculations. Therefore, minimizing the data movement costs of different CNNs is the key to high throughput and energy efficiency.
This work will suggest how to optimize the data movement of the convolution operation, implement an efficient hardware acceleration scheme, and effectively manage the data flow (Data Flow), because if the Convolution data stream is not optimized before the hardware design, the final hardware accelerator will be difficult. Effectively use data and manage mobile data, and demonstrate the proposed CNN acceleration scheme and architecture by implementing LeNet end-to-end reasoning while optimizing data reuse to improve performance. The total CNN throughput of this architecture is 7.4 GOPS.

目錄
第一章 引言 1
一、深度學習 2
二、CNN人工神經網路 5
三、硬體加速 7
(一) ACCELERATION OF CONVOLUTIONAL LOOPS 8
四、論文組織 18
第二章 基於CNN神經網路的硬體加速和文獻 19
一、CNN硬體加速器相關文獻介紹 20
(一) Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks 20
(二) Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA 22
(三) Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks 25
(四) An Architecture to Accelerate Convolution in Deep Neural Networks 27
(五) A Fast FPGA-based Deep Convolutional Neural Network Using Pseudo Parallel Memories 28
第三章 應用於CNN之Lenet神經網路模擬結果 29
一、前言 29
二、CNN神經網路之Lenet網路架構 30
三、模擬結果 34
第四章 硬體架構設計與實作 41
一、前言 41
二、硬體規格 41
三、硬體架構設計 43
四、各單元之硬體架構設計 47
(一) Data bus from buffer to PE (Data2PE) 47
(二) Convolution PE Architectrue 53
(三) Max Pooling 58
(四) Fully Connected 62
(五) Parallel Convolution PEs 64
五、實作結果 65
(一) 數位IC之設計流程 65
(二) 晶片規格 66
(三) SYNTHESIS 69
(四) Layout 72
第五章 結論 73
文獻參考 74

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