臺灣博碩士論文加值系統

本論文提出一個適用於Tiny-Yolo V2的神經網路加速器，並透過量化的策略，將輸入、輸出以及權重的資料格式轉換為uint8，以降低資料大小，達到減輕硬體資源的使用。在資料讀取上，考慮到Tiny-Yolo V2後幾層的feature map size，並無法有效使用頻寬，故本論文提出能提高bandwidth使用率的input feature maps(IF maps)資料擺放方式，並透過PE進行convolution運算以及requantize運算，得到神經網路的輸出。最後分別利用Vivado進行運算的驗證，與Design Compiler進行電路合成，得到最終的Tiny-Yolo V2的硬體加速器。

This paper proposes a neural network accelerator for Tiny-Yolo V2, and converts the data formats of input, output, and weight to uint8 through a quantization strategy to reduce the data size and make the hardware utilization more efficient. Since the size of input feature maps(IF maps) in Tiny-Yolo V2 backend layers is not 64bit-compatible, we propose an IF maps placement method that can improve the bandwidth utilization and arrange PE to calculate convolution and quantization to obtain the output of the neural network. Finally, Vivado environment is used to verify the hardware in FPGA, and the design is synthesized by the Design Compiler to obtain the final Tiny-Yolo V2 hardware accelerator.

摘要 i
Abstract ii
目次 iii
表目次 v
圖目次 vi
第1章 緒論 1
1.1 研究動機 1
1.2 論文架構 2
第2章 文獻探討 3
2.1 先前設計 3
2.2 CNN輕量化 6
2.3 Tiny-Yolo v2 8
第3章 研究方法 10
3.1 Bandwidth分析 10
3.2 Architecture Overview 12
3.2.1 Data Placement in DRAM 13
3.2.2 SRAM 資料讀取與寫入 16
3.2.3 Data flow 23
第4章 實驗結果與討論 31
4.1 驗證資料的取得 31
4.2 硬體加速器實現與設計比較 34
4.2.1 硬體加速器FPGA驗證 34
4.2.2 硬體加速器ASIC實現 35
第5章 結論與未來工作 38
5.1 結論 38
5.2 未來工作 39
參考書目 40

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