臺灣博碩士論文加值系統

本論文提出多種適用於5T和7T靜態隨機存取記憶體的電路設計，其主要包括一記憶體陣列、複數個控制電路、複數個預充電電路、一待機啟動電路、複數個字元線電壓位準轉換電路以及複數個高電壓位準控制電路，該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成，每一列記憶體晶胞設置一個控制電路，5T SRAM每一記憶體晶胞係包括一第一反相器（由一PMOS電晶體P11與一NMOS電晶體N11所組成）、一第二反相器（由一PMOS電晶體P12與一NMOS電晶體N12所組成）及一存取電晶體（由NMOS電晶體N13所組成），7T SRAM每一記憶體晶胞係包括一第一反相器（由一PMOS電晶體P11與一NMOS電晶體N11所組成）、一第二反相器（由一PMOS電晶體P12與一NMOS電晶體N12所組成）、一存取電晶體（由NMOS電晶體N13所組成）、以及讀取用電晶體N14和N15。每一控制單元係連接至對應列記憶體晶胞中之每一記憶體晶胞的NMOS電晶體N11的源極以及NMOS電晶體N12的源極，以便因應不同操作模式而控制NMOS電晶體N11和N12的源極電壓，寫入模式時，對於NMOS電晶體N11的源極而言，有三種電路態樣設計，藉由比接地高的電壓、斷路或維持接地電壓但配置較小通道寬長比之NMOS電晶體N11和N12，以上三種方法可有效避免習知具單一位元線之單埠SRAM存在寫入邏輯1相當困難之問題；讀取模式時，設計成兩階段讀取，於讀取第一階段時，藉由比接地電壓還低的電壓以加快讀取速度，亦避免因製程小型化，電壓差變小，而導致的速度下降，於讀取第二階段，由原本比接地電壓低的電壓改回原本的接地電壓，以避免無謂的功率消耗，另讀取時，因設置比接地低的電壓即使配置較小通道寬長比之NMOS電晶體N11和N12也不會造成誤寫入；待機模式時，藉由比接地高的電壓，以降低漏電流；保持模式時，維持原本的接地電壓。再者，藉由待機啟動電路的設計，以有效促使靜態隨機存取記憶體快速進入待機模式，並因而有效提高靜態隨機存取記憶體之待機效能。此外，藉由該複數個字元線電壓位準轉換電路以及複數個高電壓位準控制電路的設計，以有效降低5T SRAM讀取時之半選定晶胞干擾，和提高7T SRAM之讀取速度。

This paper presents a new Static Random Access Memory (SRAM) circuit design, which includes a memory array, a plurality of control circuits, a plurality of precharge circuits, a standby-start circuit, a plurality of word line voltage level conversion circuits and a plurality of high voltage level control circuits. The memory array is composed of plural column cells and plural row cells, each row cell having a control circuit and a word line voltage level conversion circuit, and each column cell having a precharge circuits and a high voltage level control circuit. In Five-Transistor SRAM(5T SRAM), each memory cell includes a first inverter, including a PMOS transistor P11 and a NMOS transistor N11, a second inverter, including a PMOS transistor P12 and a NMOS transistor N12, and an access transistor N13. In Seven-Transistor SRAM(7T SRAM), each memory cell includes a first inverter, including a PMOS transistor P11 and a NMOS transistor N11, a second inverter, including a PMOS transistor P12 and a NMOS transistor N12, an access transistor N13, and reading transistors N14 and N15. Each control circuit is connected to the source electrodes of NMOS transistor N11 and N12 of each memory cell of a corresponding row cell, so as to control the source voltages of NMOS transistor N11 and N12 according to different operation modes. In writing mode, there are three kinds of circuit configurations of the source electrode of NMOS transistor N11: higher than ground voltage, opened circuit and keeping ground voltage but configured with smaller channel width to length ratio of NMOS transistor N11 and N12. The above three circuit configurations can effectively avoid the conventional single-bit-line of a SRAM exists a problem of considerable difficulty in writing a logic 1. In the first phase of the reading mode, lower the source electrode of the 5T SRAM NMOS transistor N11 from an original ground voltage to less than the ground voltage, and lower the source electrode of the 7T SRAM NMOS transistor N12 from an original ground voltage to less than the ground voltage, to speedup reading logic 0. In the second phase of the reading mode, bring the source electrode back to the ground voltage in order to reduce unnecessary power consumption. In standby mode, raise the source electrode of the NMOS transistor N11 and N12 of whole memory cells higher than the ground voltage in order to effectively reduce the leakage current. In the holding mode, keep the source electrode of the NMOS transistor N11 and N12 in original ground voltage. Furthermore, with the standby-start circuit is designed to effectively promote SRAM quickly enter standby mode, and thus improve the effectiveness of SRAM of standby. Finally, during the reading operation, the word line voltage level conversion circuits and the high voltage level control circuits can increase the on-resistance of NMOS transistor N13 and reduce the on-resistance of the NMOS transistor N11, and thus reduce the semi-selected cell disturbance of 5T SRAM and improve reading speed of 7T SRAM.

摘 要 I
Abstract III
誌謝 V
目錄 VI
表目錄 VIII
圖目錄 IX
第一章 緒論 1
1.1 前言 1
1.2 研究背景與動機 1
1.3 研究目的 7
一、解決寫入邏輯1困難之問題 7
二、高讀取速度並避免無謂的功率消耗 7
三、快速進入待機模式 7
四、低待機電流 7
五、降低讀取時之半選定晶胞干擾 7
1.4本論文的組織 11
第二章 靜態隨機存取記憶體之架構 12
2.1傳統6T SRAM架構與工作原理 12
2.2傳統5T SRAM架構與工作原理 13
2.3本論文提出之靜態隨機存取記憶體的主要技術特徵 15
第三章 本論文提出之靜態隨機存取記憶體電路設計 20
3.1本論文之靜態隨機存取記憶體控制電路設計 20
一、本論文之靜態隨機存取記憶體HVL1和OVL1各有八種可能的實現電路 20
二、本論文之靜態隨機存取記憶體GVL1 控制電路設計 25
3.2本論文之靜態隨機存取記憶體的基本架構 28
3.3本論文之靜態隨機存取記憶體寫入操作 37
一、本論文之5T和7T靜態隨機存取記憶體HVL1寫入操作 37
二、本論文之5T和7T靜態隨機存取記憶體OVL1寫入操作 39
三、本論文之5T和7T靜態隨機存取記憶體GVL1寫入操作 41
3.4本論文之5T靜態隨機存取記憶體讀取操作 43
一、本論文之5T靜態隨機存取記憶體HVL1讀取操作 43
二、本論文之5T靜態隨機存取記憶體OVL1讀取操作 46
三、本論文之5T靜態隨機存取記憶體GVL1讀取操作 48
3.5本論文之7T靜態隨機存取記憶體讀取操作 51
一、本論文之7T靜態隨機存取記憶體HVL1讀取操作 51
二、本論文之7T靜態隨機存取記憶體OVL1讀取操作 54
三、本論文之7T靜態隨機存取記憶體GVL1讀取操作 56
3.6本論文之5T靜態隨機存取記憶體待機模式 58
一、本論文之5T靜態隨機存取記憶體HVL1待機模式 58
二、本論文之5T靜態隨機存取記憶體OVL1待機模式 61
三、本論文之5T靜態隨機存取記憶體GVL1待機模式 62
3.7本論文之7T靜態隨機存取記憶體待機模式 64
一、本論文之7T靜態隨機存取記憶體HVL1待機模式 64
二、本論文之7T靜態隨機存取記憶體OVL1待機模式 67
三、本論文之7T靜態隨機存取記憶體GVL1待機模式 69
3.8本論文之5T和7T靜態隨機存取記憶體的保持模式 70
第四章 電路模擬與討論 71
4.1本論文之靜態隨機存取記憶體的寫入模擬結果 71
一、5T和7T靜態隨機存取記憶體HVL1的寫入模擬結果 71
二、5T和7T靜態隨機存取記憶體OVL1的寫入模擬結果 72
三、5T和7T靜態隨機存取記憶體GVL1的寫入模擬結果 73
4.2本論文之靜態隨機存取記憶體的讀取模擬結果 74
一、本論文5T靜態隨機存取記憶體的讀取模擬結果 76
二、本論文7T靜態隨機存取記憶體的讀取模擬結果 78
4.3本論文之靜態隨機存取記憶體的待機模擬結果 81
一、本論文5T靜態隨機存取記憶體HVL1的待機模擬結果 81
二、本論文5T靜態隨機存取記憶體OVL1的待機模擬結果 82
三、本論文5T靜態隨機存取記憶體GVL1的待機模擬結果 83
四、本論文7T靜態隨機存取記憶體HVL1的待機模擬結果 84
五、本論文7T靜態隨機存取記憶體OVL1的待機模擬結果 85
六、本論文7T靜態隨機存取記憶體GVL1的待機模擬結果 86
第五章 結論 87
參考文獻 88

[1]Yuen H. Chan, William V. Huott and Donald W. Plass, “Eight transistor SRAM cell with improved stability requiring only one word line”, US pat. 7606060 B2, Oct. 20, 2009.
[2]Jui-Lung Chen, Yi-Hsun Chung, Chia-Chiuan Chang, and Wei-Shung Chen, “Memory System”, US pat. 7706203 B2, Apr. 27, 2010.
[3]Ming-Chuen Shiau, Chien-Cheng Yu, and En-Ghih Chang, “Single port SRAM having a lower power voltage in writing operation”, TW pat. I426515 B, Feb. 11, 2014.
[4]Ming-Chuen Shiau, Chien-Cheng Yu, and Kuan-Ting Chen, “Single port SRAM having a lower power voltage in writing operation”, TW pat. I426514 B, Feb. 11, 2014.
[5]Ming-Chuen Shiau and Wei-Che Tsai, “Single port SRAM having a discharging path”, TW pat. I419162 B, Dec. 11, 2013.
[6]Sushil Sudam SAKHARE, “Five transistor SRAM cell”, TW pat. I534802 B, May 21, 2016.
[7]Seong-Ook Jung et al., “Low-power 5T SRAM with improved stability and reduced bitcell size ”, JP Pat. No. 5478772B2, Apr. 23, 2014.
[8]Satyanand Nalam et al., “5T SRAM with asymmetric sizing for improved read stability”, IEEE Journal of Solid-State Circuits, vol. 46. no. 10, pp. 2431- 2442, Oct. 2011.
[9]I. Carlson et al. ,” A high density, low leakage, 5T SRAM for embedded caches,” Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European, pp.215-218, 2004.
[10]Ming-Chuen Shiau and Sheng-Wei Liao, “Single port SRAM having a higher voltage word line in writing operation”, TW pat. I404065 B, Aug. 1, 2013.
[11]Ming-Chuen Shiau and En-Ghih Chang “Single port SRAM with standby start-up circuit”, TW pat. I489457 B, Jun. 21, 2015.
[12]Ming-Chuen Shiau and En-Ghih Chang, “5T single port SRAM”, TW pat. I436359 B, May 1, 2014.
[13]Ming-Chuen Shiau and En-Ghih Chang, “5T SRAM”, TW pat. I433151 B, Apr. 1, 2014.
[14]Ming-Chuen Shiau, Chien-Cheng Yu, and Kuan-Ting Chen, “Single port SRAM with reducing standby current”, TW pat. I425510 B, Feb. 1, 2014.
[15]Ming-Chuen Shiau and En-Ghih Chang, “Dual port SRAM with standby start-up circuit”, TW pat. I478164 B, Mar. 21, 2015.
[16]Ming-Chuen Shiau and En-Ghih Chang, “High performance SRAM”, TW Pat. No. I451414B, Sep. 1, 2014.
[17]Chua-Chin Wang, Chiang-Hsiang Liao, and Sih-Yu Chen, “A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40 nm process,” in Proc. International Symposium on Circuits and Systems, pp. 1126-1129, June 2014.
[18]S. Akashe, S. Bhushan, and S. Sharma, “High density and low leakage current based 5T SRAM cell using 45 nm technology,” in Proc. International Conference on Nanoscience, Engineering and Technology (ICONSET), Nov. 2011, pp. 346-350.
[19]Ming-Chuen Shiau, Ying-Xin Jhang, Yen-Ting Lin, and Chia-Chen Hsu, “Dual port sram having a discharging path”, TW Pat. No. M393773, Dec. 1, 2010.
[20]Jui-Lung Chen, Gia-Hua Hsieh, Yi-Hsun Chung, Chia-Chiuan Chang, Yu-Chih Yeh, and Ho-Hsiang Chen, “Static random access memory”, TW Pat. No. I307890B, Mar. 21, 2009.
[21]Osamu Hirabayashi, “Static random access memory (SRAM) with clamped source potential in standby mode”, US pat. 7382674 B2, Jun. 3, 2008.
[22]Osamu Hirabayashi, “Static random access memory device and method of reducing standby current”, US pat. 7254085 B2, Aug. 7, 2007.
[23]Tae-Joong Song and Jae-Seung Choi, “SRAM employing virtual rail scheme stable against various process-voltage-temperature variations”, US Pat. No. 7110317B2, Sep. 19, 2006.
[24]Tae-Hyoung Kim et al., “A Voltage Scalable 0.26 V, 64 kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode”, IEEE Journal of Solid-State Circuits, vol. 64, pp. 1785 - 1795, 2009.
[25]Ding-Ming Kwai, “Modeling of SRAM Standby Current by Three-Parameter Lognormal Distribution”, Design, and Testing, 2009. in Proc. IEEE International Workshop on Memory Technology (MTDT '09), Aug. 31-Sept. 2, 2009, pp. 77 – 82.
[26]Scott T. Becker, “Negatively charged wordline for reduced subthreshold current”, US pat. 6865119 B2, Mar. 8, 2005.