|
[1] W. M. Reddick and G. A. J. Amaratunga, “Silicon surface tunnel transistor,” Applied Physics Letters, vol. 67, no. 4, pp. 494–496, 1995. [2] C. W. Yeung, A. Padilla, T. J. King Liu, and C. Hu, “Programming characteristics of the steep turn-on/off feedback FET (FBFET),” in VLSI Symp. Tech. Dig., 2009, pp. 176–177. [3] Savio, S. Monfray, C. Charbuillet, and T. Skotnicki, “On the limitations of silicon for I-MOS integration,” IEEE Trans. Electron Devices, vol. 56, no. 5, pp. 1110–1117, May 2009. [4] H. Kam, D. T. Lee, R. T. Howe, and T. J. King, “A new nano-electromechanical field effect transistor (NEMFET) design for low-power electronics,” in IEDM Tech. Dig., 2005, pp. 463–466. [5] D. Hisamoto, S.I. Saito, A. Shima, H. Yoshimoto, K. Torii, and E. Takeda, “CxFET: A novel steep subthreshold swing CMOS featuring a tunnel-injection bipolar transistor and MOSFET device complex” in IEDM Tech. Dig., p. 233-236, 2011. [6] A. Mallik and A. Chattopadhyay, “Tunnel field-effect transistors for analog/mixed-signal system-on-chip applications,” IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 888–894, Apr. 2012. [7] Y. Khatami and K. Banerjee, “Steep subthreshold slope n- and p-type tunnel-FET devices for low-power and energy-efficient digital circuits,” IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2752–2761, Nov. 2009 [8] A. Asenov, “Random dopant induced threshold voltage lowering and fluctuations in sub 0.1 m MOSFETs: A 3D ‘atomistic’ simulation study,” IEEE Trans. Electron Devices, vol. 45, pp. 2505–2513, 1998. [9] T. Mizuno, J. Okamura, and A. Toriumi, “Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET’s,” IEEE Trans. Electron Devices, vol. 41, pp. 2216–2221, 1994. [10] P. A. Stolk and D. B. M. Klaasen, “The effect of statistical dopant fluctuations on MOS device performance,” in IEDM Tech. Dig., 1996, pp. 627–630 [11] A. Asenov, S. Kaya, and A. R. Brown, “Intrinsic parameter fluctuation in decananometer MOSFETs introduced by gate line edge roughness,” IEEE Trans. Electron Devices, vol. 50, no. 5, pp. 1254–1260, May 2003. [12] A. Asenov, S. Kaya, and J. H. Davies, “Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations,” IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 112–119, Jan. 2002. [13] A. R. Brown, N. M. Idris, J. R. Watling, and A. Asenov, ”Impact of metal gate granularity on threshold voltage variability: a full-scale three dimensional statistical simulation study,” IEEE Electron Device Lett., Vol.31, Iss.11, pp.1199-1201, Nov. 2010. [14] T. Matsukawa, S. O’uchi, K. Endo, Y. Ishikawa, H. Yamauchi, Y. X. Liu, J. Tsukada, K. Sakamoto and M. Masahara, ”Comprehensive analysis of variability sources of FinFET characteristics,” in VLSI Symp. Tech. Dig., pp. 118-119, 2009. [15] G. Leung and C. O. Chui, “Stochastic variability in silicon double gate lateral tunnel field-effect transistors,” IEEE Trans. Electron Device, vol. 60, no. 1, pp. 84–91, Jan. 2013. [16] U. E. Avci, R. Rios, K. Kuhn, I. A. Young, “Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic,” VLSI Technology (VLSIT), 2011 Symposium on, pp. 124-125, 2011. [17] V. Saripalli, S. Datta, V. Narayanan, and J. P. Kulkarni,“Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design,” Nanoscale Architectures, IEEE International Symposium on, 2011, pp. 45–52. [18] T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, “Doublegate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and< 60 mV/dec subthreshold slope,” in IEDM Tech. Dig., 2008, pp. 947–949. [19] ”Sentaurus TCAD, E2010-12 Manual,” Sentaurus Device, 2010. [20] A. Tura and J. C. S. Woo, “Performance comparison of silicon steep subthreshold FETs,” IEEE Trans. Electron Device, vol. 57, no. 6, pp. 1362–1368, Jun. 2010. [21] C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, “A physically based mobility model for numerical simulation of nonplanar devices,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 1164–1170, 1988. [22] C.-Y. Chang, T.-L. Lee, C. Wann, L.-S. Lai, H.-M. Chen, C.-C. Yeh, C.-S. Chang, C.-C. Ho, J.-C. Sheu, T.-M. Kwok, F. Yuan, S.-M. Yu, C.-F. Hu, J.-J. Shen, Y.-H. Liu, C.-P. Chen, S.-C. Chen, L.-S. Chen, L. Chen, Y.-H. Chiu, C.-Y. Fu, M.-J. Huang, Y.-L. Huang, S.-T. Hung, J.-J. Liaw, H.-C. Lin, H.-H. Lin, L.-T. S. Lin, S.-S. Lin, Y.-J. Mii, E. Ou-Yang, M.-F. Shieh, C.-C. Su, S.-P. Tai, H.-J. Tao, M.-H. Tsai, K.-T. Tseng, K.-W. Wang, S.-B. Wang, J. J. Xu, F.-K. Yang, S.-T. Yang, and C.-N. Yeh, “A 25-nm gate-length FinFET transistor module for 32 nm node,” in IEDM Tech. Dig., pp. 293-296, 2009. [23] A. Trivedi, S. Carlo, and S. Mukhopadhyay, “Exploring tunnel-FET for ultra low power analog applications: A case study on operational transconductance amplifier,” Design Automation Conference (DAC), 2013. [24] A. Mallik and A. Chattopadhyay, “Drain-dependence of tunnel field-effect transistor characteristics: The role of the channel,” IEEE Trans. Electron Devices, vol. 58, no. 12, pp. 4250–4257, Dec. 2011. [25] S. Mookerjea, R. Krishnan, S. Datta, and V. Narayanan, “On enhanced Miller capacitance effect in interband tunnel transistors,” IEEE Electron Device Lett., vol. 30, no. 10, pp. 1102–1104, Oct. 2009. [26] Y. Yang, X. Tong, L.-T. Yang, P.-F. Guo, L. Fan, and Y.-C. Yeo, “Tunneling field-effect transistor: Capacitance components and modeling,” IEEE Electron Device Lett., vol. 31, no. 7, pp. 752–754, Jul. 2010. [27] S.-H. Chou, M.-L. Fan, and P. Su, “Investigation and comparison of work function variation for FinFET and UTB SOI devices using a Voronoi approach,” IEEE Trans. Electron Devices, vol. 60, no. 4, pp. 1485–1489, Apr. 2013. [28] W. Long, H. Ou, J.-M. Kuo, and K. K. Chin, “Dual material gate (DMG) field effect transistor,” IEEE Trans. Electron Devices, vol. 46, pp. 865–870, May 1999. [29] W. Long and K. K. Chin, “Dual material gate field effect transistor (DMGFET),” in IEDM Tech. Dig., 1997, pp. 549–552. [30] S. Saurabh and M. Jagadesh Kumar, “Novel attributes of a dual material gate nanoscale tunnel field-effect transistor,” IEEE Trans. on Electron Devices, Vol. 58, No. 2, pp. 404-410, Feb. 2011. [31] F. Conzatti, M. G. Pala, and D. Esseni, “Surface-roughness-induced variability in nanowire InAs tunnel FETs,” IEEE Electron Device Lett., vol. 33, no. 6, pp. 806–808, Jun. 2012. [32] ITRS Roadmap, 2012 Edition. (2012)
|