臺灣博碩士論文加值系統

參數萃取方法之建立對於模擬的準確性相當重要，過去，晶圓廠所提供給客戶的元件樣本佈局(sample layout)中，Source和Body是連接在一起的即三端電晶體(3T)，其所搭配的模型(model card)也是依據此而作出。但是電路設計者實際使用元件進行設計時，並不一定會將S和B兩端連在一起。因此，現在晶圓廠傾向於直接提供給客戶四端電晶體(4T)的樣本佈局，其所搭配的模型也是針對此情況而製作，以更符合電路設計者實際使用元件的方式。為了能夠提供準確無誤的模型給電路設計者使用，可靠的參數萃取方法的建立就更加被彰顯出其重要性。
本論文使用的3T與4T NMOS元件同樣置於雙埠(2-port)的pad上來進行RF量測與參數萃取的工作。本研究對於2-port量測的de-embedding方法以及參數萃取的方法作了一系列詳盡的探討，並且將所萃取出來的參數值代回小訊號模型加以驗證模型的可靠性與準確性，有了正確的小訊號模型表示我們能夠萃取出正確的參數值，正確的參數值可以提供我們方向與思維來製作更好的model。
論文的最後再針對寄生電容作一連串詳細討論，分別從模擬(Raphael Simulator)與手算分析兩方面進行，結果顯示手算分析與模擬相當吻合，表示整個應用於計算過程中的想法相當正確，手算分析建立的成功讓我們可以準確地估算出特定結構的寄生電容，值得一提的是，本論文的手算電容分析的計算方式較其他參考文獻為直接也較為簡便。

Parameter extraction method development is very important for accuracy of simulation. In the past, foundries always provide customers with the 3T sample layout, whose source and body terminals are connected together. But foundries tend to provide customers with 4T sample layout for circuit designers’ purpose at present. And model card is constructed on 4T device to match the practical using way of circuit designers. In order to provide circuit designers with accurate model card, reliable parameter extraction method development is obviously important.
3T and 4T device in the thesis are put in 2-port pad to do RF measurement and parameters extraction. In this thesis, 2-port de-embedding and parameters extraction methods have been discussed in detail and used extracted parameters to verify the reliability and accuracy of small signal equivalent model. Obtaining correct small signal equivalent model represents that we can extract correct parameter values which could provide us with direction and thought to construct better model card.
The last part of this thesis is detailed discussion of parasitic capacitances. The results reveal that the simulation and analytical calculated are very matched. This represents the thought applied to calculating process is very correct. The success of analytical calculated model can accurately estimate the parasitic capacitances of specific structure. It is worthy to mention that the calculating method is more direct and simpler than other published references.

中文摘要………………………………………………………………………………………..i
Abstract………………………………………………………………………………………..ii
誌謝..............................................................................................................................iii
Contents………………………………………………………………………………………iv
Figure Captions……………………………………………………………………………..vii
Table Captions…………………………………………………………………………….....xi
Chapter1 Introduction……………………………………………………………………….1
1.1 Motivation and Background....……………………………………………………1
1.2 Thesis organization………………………………………………………………..3
Chapter2 3T and 4T RF MOSFET Layout and Application………………………………5
2.1 Layout……………………………………………………………………………….5
2.2 Application………………………………………………………………………….6
Chapter3 RF MOSFET Small Signal Equivalent Circuit Model Analysis.....……………7
3.1 Preface…………………………………………………………............................7
3.2 3T MOSFET under linear and saturation regions.................………………….7
3.2.1 Linear region.......................................…………………………………..7
3.2.2 Saturation region............................…………………………………….11
3.3 4T MOSFET under linear and saturation regions……………………………13
3.4 Comparison between 3T and 4T MOSFET...................................................13
3.4.1 Substrate network......……………………………………………………13
3.4.2 Parasitic resistance, capacitance, inductance……………………….14
3.4.3 De-embedding method………………………………………………14
Chapter4 3T RF MOSFET Model Parameter Extraction………………………………..20
4.1 De-embedding methods....……………………………………….....................20
4.1.1 Open de-embedding…………………………………….......................20
4.1.2 Short de-embedding..........................................................................21
4.2 Parasitic resistance and inductance extraction and analysis………………..22
4.2.1 Parasitic RL extraction from short pad……………………………….22
4.2.2 Parasitic RL extraction from device…………………………………….24
4.2.3 Frequency and bias dependence…………………………………….30
4.2.4 Device geometry dependence.......…………………………………….31
4.3 Capacitance extraction and analysis…………………………………………...32
4.3.1 Bias dependence…………………………………………………….......33
4.3.2 Frequency dependence……………………………………………........35
4.3.3 Device geometry dependence………………………………………….36
Chapter5 4T RF MOSFET Model Parameter Extraction………………………………..45
5.1 De-embedding methods....…………………………….....................…………45
5.2 Parasitic resistance and inductance extraction and analysis………………..45
5.2.1 Parasitic RL extraction from device…………………………………….46
5.2.2 Frequency and bias dependence…………………………………….49
5.2.3 Device geometry dependence.......…………………………………….50
5.3 Capacitance extraction and analysis…………………………………………...50
5.3.1 Bias dependence…………………………………………………….......51
5.3.2 Revised method to extract capacitance………………………………54
5.3.3 Frequency dependence……………………………………………........57
5.3.4 Device geometry dependence………………………………………….57
Chapter6 Small Signal Model Verification by Equivalent Circuit Simulation…………71
6.1 Comparison of measured and simulation for 3T device………………………71
6.1.1 Linear regions for 3T device…………………………………………..71
6.1.2 Saturation regions for 3T device……………………………………74
6.2 Comparison of measured and simulation for 4T device………………………76
6.2.1 4T device in linear regions………………………………………….......77
6.2.2 4T device in Saturation regions………………………………………...79
6.3 The role of substrate parameters in equivalent circuit………………………..81
Chapter7 Future Work…………………………………………………………………….104
7.1 Parasitic resistance extracted from short pad………………………………..104
7.2 Bulk resistance and capacitance extraction………………………………….104
7.3 Small signal equivalent circuit modification…………………………………..105
Reference………………………………..………………………………………………106

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