臺灣博碩士論文加值系統

近年來，離散小波轉換（DWT）已被應用於許多方面，這些應用包括了訊號處理、影像處理、數字分析、統計與醫學等。相對於其他的基底轉換法（如：快速傅立業轉換（Fast Fourier Transform；FFT）或離散餘弦轉換（Discrete Cosine Transform；DCT）等…），DWT有著下列的優點：1. 提供了適應性的時間與頻率解析能力、2. 降低訊號處理時的失真度、3. 一維小波轉換的計算複雜度為O(N)（N代表取樣資料的個數）4. 可以有效的落實在VLSI的設計。基於以上的優點，小波轉換法相當適合在規劃資料的分析與計算。
小波轉換的相關研究與資料已經非常的廣泛，無論是學術上的數學理論推導或硬體設計與驗證都可於許多地方查詢得到；但為了面對日趨龐大、複雜的積體電路設計需求，設計符合可重複使用（Reusable）的智慧財產（Silicon Intellectual Properties；SIP）已成了積體電路工業的因應之道。因此，本論文以可重複使用為前提，設計一個一維小波轉換的IP。而於我們的設計中，我們考慮了下列重要的設計因素：
1.高速的運算能力：本設計詳加考慮了小波轉換的演算法，而得到一個具備快速運算的架構，而可滿足項數位攝影機的即時影像壓縮要求。
2.可程式化的設計：我們考慮了晶片設計上的可程式化，使得使用此IP 的使用者可輕易的藉由此設計，提高其精確度。再者，我們也利用數個本論文所設計的IP，在數位處理的系統上達到可程式化，以提高整體的處理速度。
3.自我測試的能力：本 IP 具備自我測試（BIST）的能力，可減少許多晶片在測試上的問題。
我們將所提的架構利用FPGA與ASIC的方法驗證，實驗結果顯示我們的設計於面積優於現有的其他架構，速度的評估在FPGA上可以達到30MHz，而使用ASIC的設計方式更可以達到100MHz，非常適合即時的語音與影像處理，而且本架構具有自我測試（BIST）的能力，而且偵錯包含率（Fault Coverage）可高達98.7%。

Recently, Discrete Wavelet Transform (DWT) has been widely used in many applications. These applications include signal processing, image processing, numerical, statistical, and medical analysis. Compared with other transforms, such as Fourier transform and discrete cosine transform (DCT), DWT has the following advantages: 1. Can provide appropriate time-frequency window, 2. Can reduce the distortion of signal analysis, 3. The complexity of computation is O(N), and 4. Can be easily implemented by VLSI design. Based on these advantages, DWT becomes very convenient for analyzing and computing the data.
Due to the increasing complexity of VLSI design, reusable silicon intellectual properties, IP, becomes one of the possible solutions for the IC industry. In this thesis, an 1D-DWT architecture has been proposed. The following important factors have been considered and implemented in the proposed design such that it can be an IP easily:
1.High-Speed: we have developed an efficient DWT algorithm such that the operational speed is satisfactory. Furthermore, the area of the proposed is minimal compared with other designs..
2.Reconfiguration: there are two ways to reconfigure the proposed design. Firstly, the data sizes of internal processing elements can be reconfigured to increase the precision, and secondly, the number of processing elements can be also changed to improve the accuracy of the data.
3.Testing: the proposed architecture is very regular, hence it is very suitable for BIST design. We have modified our design with BIST capability, such that the testing of proposed architecture becomes very simple.
The proposed architecture has been implemented by using FPGA and ASIC. Experimental results show that our area is superior to other existing DWT designs. The operational speed can be 30MHz for FPGA implementation, and 100MHz for the ASIC implementation. Hence, the design can be used for the real-time compression applications. Since BIST is integrated in the proposed design, the fault coverage can be as high as 98.7%.

目錄
摘要 ....................................................... i
致謝 ....................................................... v
目錄 ....................................................... vi
圖目錄 ..................................................... vii
1 簡介 ( Introduction )
1.1 數位影像處理 ( Digital Image Process ).............. 1
1.2 設計流程 ( Design Flow )............................ 3
2 理論 ( Theorem )
2.1 傅立葉轉換 ( Fourier Transform ).................... 6
2.2 小波轉換 ( Wavelet Transform )...................... 10
3 硬體架構( Hardware Architecture )
3.1 濾波器單元( Filter Unit )
3.1.1 乘加器模組 ( MAC Module )........................... 14
3.1.2 濾波器係數 ( Filter Coefficient )................... 17
3.1.3 輸入端延遲緩衝器模組 ( Input Delay Module )......... 19
3.1.4 資料暫存延遲緩衝器模組 ( Register Bank Module )..... 20
3.2 控制單元 ( Control Unit )........................... 21
3.3 測試考量 ( Test Strategy ).......................... 25
3.4 整體架構 ( Architecture )........................... 27
4 模擬結果 ( Simulation )
4.1 軟體驗證 ( Software Verify )........................ 30
4.2 硬體實現 ( Hardware Implement )
4.2.1 FPGA部分........................................... 34
4.2.2 ASIC部分........................................... 35
4.3 智慧財產( Soft IP )................................. 37
5 結論 ( Summary ).................................... 40
參考文獻 ( Reference )...................................... 44

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