臺灣博碩士論文加值系統

在超寬頻系統中，類比至數位轉換器的效能與功率消耗對整體系統的效率具有重要的影響。本論文著重高速類比至數位轉換器的設計考量，並提出一個應用於超寬頻系統之六位元快閃式類比至數位轉換器的設計。這個設計使用所提出的前置放大器設計方法，可在給定功率的情況下達到最高的頻寬，並且利用所提出比較器的時脈改進方法來降低電路的非理想性。此外，本電路使用偏移消除、電容式插補、以及分散式取樣和維持技巧以解決在快閃式類比至數位轉換器設計上遭遇的問題。本設計使用台積電 0.13 微米製程實現。晶片實際量測結果顯示，在七億赫茲的取樣頻率下，有效位元數為五點三位元。消耗功率為一百一十二毫瓦，有效解析度頻寬為五億赫茲。由於高輸入頻寬以及低功率消耗，本論文中所提出之電路相當適合應用於超寬頻系統。

The performance and power consumption of analog-to-digital converters (ADCs) affect the efficiency of the ultra wideband (UWB) systems. In this thesis, we focus on the design techniques development of high speed ADCs, and propose a 6-bit high speed ADC design for the applications of UWB systems. In this design, a design methodology for pre-amplifier is used to achieve the maximum bandwidth while consuming the fixed power. Also, the non-ideality of comparators can be suppressed by improving the comparator’s timing. This proposed design adopts the offset cancellation, capacitive interpolation and distributed sample-and-hold techniques to solve the problems in designing flash ADCs. This proposed ADC is designed in TSMC 0.13�慆 process, and the experimental results show that the effective number of bit (ENOB) is 5.3 in the sampling frequency of 700MHz. The power consumption is 112mW, and the resolution bandwidth (ERBW) is 500MHz. Due to the high input bandwidth and low power consumption, this ADC is very suitable to UWB systems.

List of Figures ix
List of Tables xi
Chapter 1 Introduction 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 4
Chapter 2 Basics of High-Speed Analog-to-Digital Converters 5
2.1 FLASH ADC 6
2.2 TWO-STEP ADC 8
2.3 SUB-RANGING ADC 9
2.4 FOLDING ADC 11
2.5 PIPELINED ADC 13
2.6 TIME-INTERLEAVED ADC 15
2.7 CONCLUSION 17
Chapter 3 Design Techniques for Flash ADCs 18
3.1 AUTOZEROING 18
3.2 SAMPLE-AND-HOLD 20
3.3 INTERPOLATION 24
3.3.1 Resistive Interpolation 27
3.3.2 Active Interpolation 28
3.3.3 Capacitive Interpolation 29
3.4 RESISTIVE INTERPOLATION 30
3.5 OFFSET CANCELLATION 36
3.5.1 Input Offset Cancellation 36
3.5.2 Output Offset Cancellation 38
3.5.3 Input and Output Offset Cancellation 40
Chapter 4 The Proposed Flash ADC 42
4.1 INTRODUCTION 42
4.2 ARCHITECTURES AND SCHEEMATICS 43
4.2.1 Distributed Sample-and-Hold 45
4.2.2 1st ~ 4th Stage Preamps 46
4.2.3 Comparators 48
4.2.4 65-to-6 ROM Encoder with Bubble Correction 50
4.2.5 Clock Generator 52
4.2.6 Clock Divider 53
4.3 GAIN CONSIDERATION 54
4.4 INTRODUCTION OF GM/ID METHOD 55
4.5 PREAMP DESIGN METHODOLOGY 56
4.6 LOW-POWER CONSIDERATION 59
4.7 7 LAYOUT 67
4.8 SIMULATION RESULTS 68
4.9 EXPERIMENTAL RESULTS 74
Chapter 5 Conclusion and Future Work 80
References 82

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