臺灣博碩士論文加值系統

在本篇論文中，我們將提出一個操作於5 ~ 6 GHz 之射頻發射機。這個電路包含了正交之升頻混波器、可變增益放大器以及輸出端之平衡-不平衡轉換器(Balun)。另外利用10 ~12 GHz壓控振盪器與除頻器產生所需之本地震盪訊號供升頻器操作。由於操作於本頻段之規格如802.11a 與802.16e，皆使用OFDM調變方式，會有發射訊號之峰均功率比(Peak-to-Average Power Ratio, PAPR)過大的問題，易造成訊號失真，因此本電路之設計重點在於：
1.利用微-混波器(Micro-Mixer)架構提升線性度
2.增加輸出功率可調範圍、輸出功率線性化數位控制，並且利用整合變壓器(integrated transformer)來達成單一輸出端。
在此電路中，首先利用升頻混波器將基頻之操作訊號轉換為射頻。之後經過可變增益放大器將升頻後之訊號放大到功率放大器所要求之強度。最後再於可變增益放大器之輸出端接上整合變壓器將電路之雙端輸出改為單端的訊號，以方便將來接上功率放大器。此變壓器同時扮演可變增益放大器之輸出阻抗以及將高阻抗轉為低阻抗之角色，因此可以非常容易地將最後之輸出匹配至50歐姆。
在升頻混波器中，我們採用Class-AB之 MicroMixer架構，以此方法提升電路處理大訊號之能力，增進線性度。此外我們並利用交叉耦合之方式 (cross-couple)使電路對稱性更佳。在可變增益放大器中，電路分為兩級放大以達到夠大之動態範圍，第一級為控制增益之處，利用四位元之控制訊號將所有動態範圍分為十六級，使每一級之增益達到對數線性的改變，易於控制。而可變增益放大器第二級的輸出端使用on-chip之balun，不僅可將可變增益放大器之雙端輸出轉為單端，並可以同時擔任可變增益放大器之輸出負載以及輸出50歐姆之匹配。最後與實驗室之壓控震盪器以及除頻器整合，即一射頻發射器。

A 5~ 6 GHz CMOS transmitter front-end has been designed in this work. This design contains I, Q up-conversion mixers and a VGA followed by an on-chip balun. I, Q mixers translate the baseband signal to a required frequency band and perform signal addition of in-phase and quadrature signal. The up-converted signal is amplified by a VGA to raise the output power level. Then a balun is added at the output for differential-to-single conversion. In order to process the large signals from baseband without saturating the circuit, the front-end demands high linearity performance. Besides, since in this frequency band, the standards such as 802.11a and 802.16e both apply the OFDM modulation scheme, the OFDM signal displays a high Peak-to-Average Power Ratio (PAPR) which sets extra requirement for linearity performance. Therefore, the major concern of this design is linearity such as high third order rejection and high OIP3.
In the up-conversion mixer, we implement the MicroMixer structure. The class-AB topology improves the linearity of the circuit. To gain further bisymmetric baseband signals, the proposed transconductance stage is formed with a cross-coupled type. In VGA, we control the gain with four bits control words and these 16 gain steps are linear-in-dB. At the output of the VGA, an on-chip balun is employed for differential-to-single conversion. It also provides the output loading for the VGA and the low impedance at the output for 50 ohm matching. The whole circuit is integrated with a VCO and a divider as LO signal and it process very good performance in linearity.

Abstract ………………………………………………………………………..….. I
Contents ………………………………………………………………….……… III
List of Tables ………………………………………………………….…………… VI
List of Figures ………………………………………………………………….. VII

Chapter 1 Introduction …………….…………………………………………......... 1
1.1 Motivation ………………………………………………………………….. 1
1.2 Transmitter Architecture ……………………………………………………. 2
1.3 Thesis Organization ………………………………………………………… 4

Chapter 2 On-chip Transformer …………………………………………………. 5
2.1 Introduction to On-chip Transformers ……………………………………… 5
2.1.1 Quality Factor (Q) …………………………………………………... 5
2.1.1.1 Parallel R&L Network ...……………………………………... 8
2.1.1.2 Series R&L Network ………………………………………… 8
2.1.1.3 Parallel and Series R&C Network …………………………… 9
2.1.2 Q Factor of LC Tank ………………………………………………… 9
2.1.3 Modeling …………………………………………………………. 11
2.1.3.1 Physical Layout …………………………………………… 11
2.1.3.2 Physical Model ……………………………………………... 13
2.1.3.3 Inductor Model ……………………...……………………… 14
2.1.3.4 Transformer Model …………………………………………. 18
2.1.4 Figure-of-Merit for RF Transformers ……………………………… 20
2.2 Transformer Layouts …………………………………………………….... 22
2.3 Realization and Simulation of Transformers ……………………………… 24
2.3.1 Turn Ratio: 2-to-2 ………………………………………………….. 25
2.3.2 Turn Ratio: 1-to-3 ………………………………………………….. 27
2.4 Conclusion ………………………………………………………………… 30
References …………………………………………………………………….. 31

Chapter 3 Up-conversion Mixer …………………………………………………. 33
3.1 Introduction to Mixer ……………………………………………………... 33
3.1.1 Transconductance Mixer …………………………………………... 34
3.1.2 Drain Mixer ………………………………………………………... 34
3.1.3 Resistive Mixer ……………………………………………………. 34
3.2 Mixer Fundamentals ………………………………………………………. 35
3.2.1 Conversion Gain …………………………………………………... 37
3.2.2 Noise Figure ……………………………………………………….. 37
3.2.3 1-dB Compression Point …………………………………………... 38
3.2.4 Third-Order Intercept Point ……………………………………….. 40
3.2.5 Image Cancellation ………………………………………………… 45
3.3 LO Power Requirement …………………………………………………… 47
3.4 Mixer Topology …………………………………………………………… 47
3.4.1 Single-Balanced and Doubled-Balanced Mixer …………………… 48
3.4.2 MicroMixer ………………………………………………………... 50
3.5 Circuit Design of Up-Conversion Mixer …………………………………. 51
3.5.1 Core Circuit Design ……………………………………………….. 52
3.5.2 Output Impedance and Frequency Response ……………………… 54
3.5.3 Output Buffer ……………………………………………………… 56
3.5.4 Up-Conversion Mixer with One Path ……………………………… 57
3.6 Simulation Results ………………………………………………………… 57
3.6.1 IQ Mixer …………………………………………………………… 58
3.6.2 Mixer with One Path ………………………………………………. 61
3.7 Layout of Up-Conversion Mixer ………………………………………….. 63
3.7.1 Layout Guidelines …………………………………………………. 64
3.8 Measurement Results ……………………………………………………... 66
3.8.1 Measurement Results of Up-Conversion Mixer with IQ Paths …… 66
3.8.2 Measurement Results of Up-Conversion Mixer with One Path …... 75
References …………………………………………………………………….. 77

Chapter 4 Variable Gain Amplifier …………………...…………………………. 79
4.1 Introduction to VGA ………………………………………………………. 79
4.1.1 Topology of VGA ………………………………………………….. 80
4.1.2 Linear-in-dB ……………………………………………………….. 82
4.2 Circuit Design of Digitally-Controlled VGA …………………………...… 83
4.2.1 Core Circuit Design ………………………………………………... 83
4.2.2 Gain Range ………………………………………………………… 84
4.2.3 Digital Control Part ………………………………………………... 85
4.2.4 Decision of the Value of the Current Source ………………………. 86
4.2.5 The Channel Length Modulation Effect …………………………… 87
4.2.6 Thermometer Code ………………………………………………… 89
4.2.7 The Linearity Improvement ………………………………………... 91
4.2.8 Process Variation …………………………………………………... 92
4.3 On-chip Transformer at the Output ……………………………………….. 93
4.4 Layout and Measurement Result …………………………………..…….. 100
4.4.1 VGA Test Key ……………………………………………………. 100
4.4.2 Digitally-controlled VGA ……………………………………….... 102
References …………………………………………………………………… 107

Chapter 5 RF Transmitter ………………………………………………………. 109
5.1 Transmitter Architecture ......................................................................…... 109
5.2 Circuit Block in the Transmitter …………………………………………. 110
5.2.1 Design of VCO …………………………………………………… 110
5.2.2 Divider Schematic ………………………………………………... 113
5.3 Simulation Results ……………………………………………………….. 114
5.4 Layout and Performance of RF Transmitter ……………………………... 116
References …………………………………………………………………… 118
Chapter 6 Conclusion …………………………………………………………... 119

Chapter 2:
[1] J. J. Zhou, and D. J. Allstot, “Monolithic transformers and their applications in a differential CMOS RF low-noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, pp. 2020-2027, 1998.
[2] W. Simburger, H.-D. Wohlmuth, P. Weger, and A. Heints, “A monolithic transformer coupled 5-W silicon power amplifier with 59% PAE at 0.9 GHz,” IEEE J. Solid-State Circuits, vol. 34, pp. 1881-1892, Dec. 1999.
[3] J. P. Maligeorgos, J. R. Long, “A low-voltage 5.1-5.8 GHz image-reject receiver with wide dynamic range,” IEEE J. Solid-State Circuits, vol. 35, pp. 1917-1926, Dec. 2000.
[4] W. Bakalski, W. Simburger, R. Thüringer, H.-D. Wohlmuth, and A. L. Scholtz, “A fully integrated 4.8-6 GHz power amplifier with on-chip output balun in 38 GHz-fT Si-Bipolar,” IEEE MTT-S Int. Microwave Symp. Dig. June 2003, pp.695- 698.
[5] A. M. Niknejad, and R.G. Meyer, “Analysis, design, and optimization of spiral inductors and transformers for Si RF IC’s,” IEEE J. Solid-State Circuits, vol. 33, pp. 1470-1481, Oct. 1998.
[6] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J. Solid-State Circuits, vol. 35, pp. 1368-1382, Sep. 2000.
[7] A. Zolfaghari, A. Chan, and B. Razavi, “Stacked inductors and transformers in CMOS Technology,” IEEE J. Solid-State Circuits, vol. 36, pp. 620-628, April 2001.
[8] T. H. Lee, “The design of CMOS radio-frequency integrated circuits,” Cambridge University Press, Cambridge, 1998.
[9] D. Kehrer, “Design of Monolithic Integrated Lumped Transformers in Silicon- based Technologies up to 20 GHz,” Institut f¨ur Nachrichten- und Hochfrequenztechnik der TU Wien, 2000.

Chapter 3:
[1] P. J. Sullivan, B. A. Xavier, and W. H. Ku, “A Common Source Input Cross Coupled Quad CMOS Mixer,” Analog Integrated Circuits and Signal Processing, 19, 181-188, 1999.
[2] Barrie Gilbert, “The MICROMIXER: A Highly Linear Variant of the Gilbert Mixer Using a Bisymmetric Class-AB Input Stage,” IEEE J. SOLID-STATE CIRCUITS, VOL. 32, NO. 9, SEPTEMBER 1997
[3] Kwang-Jin Koh, Mun-Yang Park, Cheon-Soo Kim, “Subharmonically Pumped CMOS Frequency Conversion (Up and Down) Circuits for 2-GHz WCDMA Direct-Conversion Transceiver,” IEEE J. SOLID-STATE CIRCUITS, VOL. 39, NO. 6, JUNE 2004
[4] Behzad Razavi, “RF Microelectronics,” Upper Saddle River, New Jersey: Prentice Hall, 1998.

Chapter 4:
[1] J. Duque-Carrilo, et al., “VERDI: an acoustically programmable and adjustable CMOS mixed-mode signal processor for hearing aid applications,” IEEE J. SOLID-STATE CIRCUITS, Vol. 31, pp. 634-645, May 1991.
[2] R. Harjani, “A low-power CMOS VGA for 50 Mb/s disk drive read channels,” IEEE Trans. Circuit Syst. II, vol. 42, pp. 370-376, June 1995.
[3] A. Motamed, C. Hwang, and M, Ismail, “A low-voltage and low-power wide-range CMOS variable-gain amplifier,” IEEE Trans. Circuit Syst. II, vol. 45, no. 7, pp. 800-811, July 1998.
[4] M. Mostafa, H. Elwan, A. Bellaour, B. Kramer, S. Embabi, “A 110 MHz 70 dB CMOS variable-gain amplifier,” IEEE Int. Symp. On Circuits and Syst., pp. 628-631, May 1999.
[5] R.G. Meyer and W.D. Mack, "A DC to 1-GHz Differential Monolithic Variable-Gain Amplifier," IEEE J. SOLID-STATE CIRCUITS, Vol. 26, No. 11, pp. 1673-1680, Nov. 1991.
[6] J. Akagi, et.al., "AIGaAs/GaAs HBT Receiver ICs for a 10 Gbps Optical Communication System," IEEE GaAs IC Symp. Dig., New Orleans, Louisiana, 1990.
[7] K.W. Kobayashi, et.al., "Monolithic GaAs HBT P-i-n Diode Variable Gain Amplifiers, Attenuators, and Switches," IEEE Trans. on MTT, Dec. 1993.
[8] K.W. Kobayashi, el.al., " HBT Low Power Consumption 2-4.6 GHz Variable Gain Feedback Amplifier," IEEE GaAs IC Symp. Dig., Miami, FL., 1992.
[9] W. C. Song, C. J. Oh, G. H. Cho, and H. B. Jung, “High frequency/high dynamic range CMOS VGA,” IEEE Electronics Letters, vol. 36, no. 13, pp. 1096-1098, June 2000.
[10] T. Yamaji, N. Kanou, and T. Itakura, “A temperature-stable CMOS variable-gain amplifier with 80-dB linearity controlled gain range,” IEEE J. SOLID-STATE CIRCUITS, vol. 37, pp. 553-558, May 2002.
[11] H. O. Elwan and M. Ismail, “Digitally programmable decibel-linear CMOS VGA for low-power mixed signal applications,” IEEE Trans. Circuit Syst. II, vol. 47, pp. 388-398, May 2000.
[12] Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High speed Physical Layer in the 5 GHz Band, IEEE Std 802.11a-1999, Sept. 1999.
[13]Broadband Radio Access Networks (BRAN); HIPERLAN Type 2; Physical layer, ETSI TS 101 475, version 1.3.1, Dec. 2001.
[14] IEEE Standard for Local and metropolitan area networks Part 16: Air Interface for Fixed Broadband Wireless Access Systems – Amendment 2: Medium Access Control Modifications and Additional Physical Layer Specifications for 2-11 GHz, IEEE Standard 802.16a-2003, April 2003.

Chapter 5:
[1] Behzad Razavi, “RF Microelectronics,” Upper Saddle River, New Jersey: Prentice Hall, 1998.
[2] J. Craninckx, M. Steyaert, and H. Miyakawa, “A fully integrated spiral-LC CMOS VCO set with prescaler for GSM and DCS-1800 systems,” Proc. CICC, pp. 403-406, May 1997.