臺灣博碩士論文加值系統

本研究利用以壓印技術及無電鍍銀技術，來製作平面顯示器之薄膜電晶體（Thin Film Transistor,TFT）電極層結構。壓印技術是目前可以不受到光學微影的物理限制，相當受到矚目的新興製造技術，本文在壓印製程研究中，以半導體製程技術來製造壓印時所需之玻璃模仁結構，搭配目前TFT製程所使用的光阻材料（AZ-650），以玻璃模仁來壓印光阻材料，探討壓印後之光阻結構及評估此光阻材料是否適合作壓印材料。另一方面，在無電鍍鍍膜研究上，欲使用金屬中電阻值最低的銀（Ag）金屬材料來作為TFT 之電極層材料。在鍍膜技術上，本研究使用鍍膜技術液相法之無電鍍製程技術來製作TFT 電極層之結構，經實驗後已獲得一些初步成果，可以將銀金屬以無電鍍製程技術，沉積在所需之玻璃基材上。最後，以奈米壓痕量測系統，將銀薄膜做硬度、彈性係數、楊氏係數等相關的機械性質量測並與塊材（Bulk）比較。

This study presents thin film transistor (TFT) electrode structures in flat panel displays by imprint and electroless silver plating techniques. Imprint technique
is not limited to the physical properties of optical lithography. In the imprinting process, the glass mold designed for imprinting process is fabricated by semiconductor manufacturing technology to imprint photoresist (AZ-650). The material is evaluated for imprint process. In addition, at present, electrode
materials used in TFT process are aluminum (Al), chromium (Cr) and so on. In other research, the thin film plating technique adopts sputtering process to manufacture TFT electrode structures. This study uses electroless silver plating process to fabricate TFT electrode structures. The experimental result shows that the silver film can be deposited on the glass wafer by electroless plating,
The mechanical properties of the silver films such as hardness, coefficient of elasticity and Young’s module are measured by nanoindentation system,compared with the bulk materials.

目 錄
目錄...............................................I
圖目錄............................................IV
表目錄..........................................VIII
中文摘要..........................................IX
英文摘要...........................................X
第一章 緒論........................................1
1-1 研究背景.......................................1
1-2 文獻回顧.......................................3
1-2-1 壓印.........................................3
1-2-2 無電鍍銀.....................................4
1-3 研究架構.......................................6
第二章 TFT 導電層加工技術現況分析..................8
2-1 TFT 原理及結構.................................8
2-2 TFT 加工技術原理及設備.........................12
第三章 壓印技術與壓印之模仁製作....................14
3-1 奈米壓印技術現況分析...........................14
3-1-1 熱壓式奈米壓印微影技術.......................14
3-1-2 紫外光硬化奈米壓印技術.......................15
3-1-3 軟微影技術...................................16
3-1-4 雷射輔助直接壓印技術.........................16
3-1-5 步進式快閃壓印微影技術.......................17
3-2 壓印之玻璃模仁設計.............................23
3-3 半導體製程技術應用在玻璃模仁製作...............25
3-3-1 基材清洗及去水烘烤...........................26
3-3-2 濺鍍薄膜沉積.................................28
3-3-3 光阻塗佈及軟烤...............................28
3-3-4 曝光、顯影及硬烤.............................30
3-3-5 光阻去除.....................................32
3-3-6 玻璃模仁之製程設備介紹.......................32
3-4 壓印製程實驗...................................36
3-4-1 壓印製程材料介紹.............................39
3-4-2 壓印製程設備介紹.............................39
第四章 無電鍍銀之電極層製作........................44
4-1 無電鍍技術原理.................................44
4-2 無電鍍銀製程...................................48
4-3 銀電極層薄膜製作...............................50
4-3-1 表面處理.....................................50
4-3-2 純水沖洗.....................................50
4-3-3 光阻剝離.....................................51
4-3-4 電鍍處理.....................................51
4-3-5 無電鍍製程設備介紹...........................52
4-4 奈米壓痕量測於銀薄膜之應用.....................56
第五章 結果與討論..................................60
5-1 壓印之結果討論.................................60
5-2 無電鍍銀薄膜量測討論...........................66
第六章 結論與建議..................................70
6-1 結論與本文貢獻.................................70
6-2 未來展望.......................................71
參考文獻

參考文獻
[1] http://techreview.com/gen_info/pr010803.asp
[2] S. Y. Chou, P. R. krauss and P. J. Renstrom, “Imprint of sub - 25 nm vias and trenches in polymers”, Applied Physics Letters, Vol.67, No.21, pp3114-3116, 1995.
[3] S. Y. Chou, P. R. Krauss, W. Zhang, L. Guo, and L. Zhuang, “Sub-10 nm imprint lithography and applications”, Journal of Vacuum Science ＆ Technology B, Vol.15, No.6, pp2897-2904, 1997.
[4] A. Lebib, M. Natali, S. P. Li, E. Cambril, L. Manin, Y. Chen, H. M. Janssen, and R. P. Sijbesma, “Control of the critical dimension with a trilayer nanoimprint lithography procedure”, Mircoelectronic Engineering, Vol.57-58, pp411-416, 2001.
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