臺灣博碩士論文加值系統

隨著電晶體的通道長度越縮越短，傳統元件模型在高頻操作時已不準確，由於BSIM3V3模型是工業界應用於中低頻的標準電晶體模型，所以我們必須找出可以解決此問題的方法。最近許多研究證明外接基板電阻於電晶體上且對傳統的電晶體模型做修正，對於高頻的特性有大幅度的改善。本論文研究S參數在GHz對於模型參數靈敏度的影響，並藉由S參數的量測配合HSPICE電路模擬軟體，建立0.25微米金氧半互補場效電晶體的高頻模型。
除了晶片尺寸變大和信號波長接近金屬線的波長外，隨著晶片尺寸變大造成寄生電容與寄生電阻效應變大，另一方面元件又越縮越小，使得金屬連線在高密度積體電路變得十分重要。這些寄生效應，
在高頻是必須被考慮的，所以我們結合元件在高頻的特性與金屬線的寄生效應建立在高頻操作的環式震盪器電路模型。
在本論文中，高頻電晶體的尺寸通道長度為0.25μm~ 0.5μm 通道寬度為200μm，但我們的環式震盪器電路模型是用N型電晶體通道長度0.35μm、通寬長度5μm 和P型電晶體通道長度0.35μm、通道寬度10μm所建立的時間延遲模型。所以，首先我們必須建立N型電晶體通道長度0.35μm、通道寬度5μm 和P型電晶體通道長度0.35μm、通道寬度10μm的BSIM3V3電晶體模型。然後藉由量測高頻電晶體的S參數。經過電晶體尺寸轉換的計算，萃取基板電阻的值。然後將電晶體的接面電容外接，加上基板電阻。最後經過修正的BSIM3V3電晶體模型在高頻的特性有明顯改善。而且，由修正後的電晶體模型和加上金屬連線效應所組成環式振盪器的時間延遲模型，在高頻的操作，確實比傳統的電晶體所組合成的時間延遲模型來的準確。我們也可以利用此模型，去預測討論用0.25μm電晶體組成的環式振盪器在GHz操作時的結果。

As the gate lengths of silicon MOSFET’s become smaller and smaller, The conventional device model is not accurate in the GHz range. Because BSIM3v3 has been widely accepted as a standard CMOS model for low and medium frequency applications, we must find a method to solve this problem. Recent research has proposed a high frequency device model by adding a complicated substrate resistance network and modifying the BSIM3v3 source code. So we study the sensitivities of S-parameter to each model parameter at 1GHz and some guide lines are given for parameter extraction. A parameter extraction technique utilizing S-parameter data at the GHz range is finally proposed for a SPICE BSIM3V3 for RF MOSFET.
Besides, chip size increases and signal wavelengths approach interconnect wire lengths. Therefore, signal delay due to interconnect become a major concern for high-performance integrated circuits. That is because the capacitance and resistance of wires increase rapidly as chip size grows and the minimum feature size is reduced. The purpose of this project is to establish RF CMOS ring oscillators delay model and to study the sensitivity of delay time to device parameters.
The dimensions of the multi-finger type MOSFET is W/L=200μm /0.25μm~W/L=200μm/0.5μm, but we use single finger type NMOS (W/L=5μm/0.35μm) and PMOS (W/L=10μm/0.35μm)devices in ring oscillator. The extracted substrate resistance in high frequency device model for multi-finger type devices cannot be directly applied to the single finger type device in ring oscillators. First, we will establish NMOS (W/L=5μm/0.35μm) model and PMOS (W/L=10μm/0.35μm) BSIM3V3 model. Second, the substrate resistances are extracted by measuring S-parameter of the multi-finger type MOSFET. The substrate resistances for the single finger type device are subsequently calculated according to a proposed method as described in Chapter4.In general, RF modification of BSIM3V3 model significantly improves the accuracy of the high-frequency performance prediction. Furthermore, For high frequency operation, According to the simulation of ring oscillator performance based on RF MOS model, with further consideration of delay time model’s interconnection effect, the accuracy of delay time prediction is much better improved.

CHAPTER 1 Introduction........................................1
1.1 Modeling of MOS Transistors using spice....................2
1.2 CMOS performance factors...................................3
CHAPTER 2 Deep-sub-micron NMOSFET and PMOSFET Models for GHz Application....................................................4
2.1 Deep-Submircon MOS modeling...............................4
2.2 Bsim3v3 model modification and extraction procedure.......5
2.2.1 I-V Parameter Extraction................................7
2.2.2 C-V Parameter Extraction................................8
2.2.2.1 Intrinsic C-V Data measurement and Extraction..........9
2.2.2.2 Junction Capacitance measurement and Extraction.......10
2.3 NMOSFET and PMOSFET model establish......................11
2.3.1 NMOSFET and PMOSFET I-V model..........................11
2.3.2 Optimization of GHz MOSFET Model Parameter using S-parameter.....................................................16
2.2.3 Ou’s Effective Gate Resistance Model for Modification of BSIM3v3....................................................18
CHAPTER 3 VLSI Interconnect effect...........................24
3.1 Interconnection Capacitance..............................24
3.2 Interconnection Resistance...............................26
3.3 Effect on delay time.....................................27
CHAPTER 4 High Speed CMOS Ring Oscillator modeling...........30
4.1 Device dimension Definitions.............................30
4.2 Delay-time Definition....................................31
4.3 CMOS Ring Oscillator Circuit modeling....................33
4.4 Delay Times simulation result............................34
4.5 Sensitivity of ring oscillator gate delay to device and process parameter............................................37
CHAPTER 5 Conclusion.........................................39

[1] Y. Cheng, et al., “BSIM3v3 Manual,” Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, 1996.
[2] BSIMPro Manual
[3] W. Liu, et al., “RF MOSFET modeling accounting for distributed substrate and channel resistance with emphasis on the BSIM3v3 SPICE model,” in IEDM, pp. 309-312, Dec. 1997.
[4] J.-J. Ou, et al., “CMOS RF modeling for GHz communication IC’s,” VLSI Symp. On Tech., Dig of Tech. Papers, pp. 94-95, June 1998.
[5] X. Jin, et al., “An Effective Gate Resistance Model for CMOS RF and Noise Modeling,” in IEDM, pp. 961-964, 1998.
[6] Yuan Taur, Fundamentals of modern VLSI devices,1998, Chap.5