臺灣博碩士論文加值系統

本論文的研究主要分成兩部份，其一是充電泵鎖相迴路連續時間模型雜訊效能的分析，其二則是充電泵鎖相迴路離散時間模型的穩定分析。
在第一部份，我們推導二階和三階充電泵鎖相迴路phase-jitter variance的上限，一開始我們利用簡單的線性模型並將來自不同雜訊源的功率頻譜密度函數予以積分，藉此得到phase-jitter variance的上限的封閉解，本文所考慮的雜訊源包含來自於壓控震盪器的相位雜訊、充電泵的雜訊、迴路濾波器的雜訊，以及參考訊號的雜訊。我們利用實驗的方式來對提出的理論加以驗證，而理論上限與實驗結果呈現相同的趨勢。
在第二部分，我們推導二階到四階充電泵鎖相迴路的線性化離散時間模型，利用一個週期內的初始條件及邊界條件，我們可以解出迴路濾波器的差分方程式，將其予以線性化並重新整理成離散時間狀態方程式，即可用來檢查穩定條件及過載條件。我們藉由模擬來驗證提出的方法，此外，為了測試迴路在不同條件下的穩定度，我們提出參考頻率下限與開路單位增益頻寬、相位邊限的經驗公式。
藉由以上的分析，希望能對工程師在設計充電泵鎖相迴路上有所幫助。

This dissertation contains two parts. One is the analysis of noise performance of charge-pump phase- locked loops (CPPLLs) under continuous-time models. The other is the stability analysis of CPPLLs using discrete-time models.
In the first part, we derive the upper bound of the phase-jitter variance of second-order and third-order CPPLLs. We employ the simple linear model in the beginning and integrate the power spectral density functions from different noise sources to determine the closed form for an upper bound of the phase-jitter variance. The noise sources we have considered in this paper are the phase noise from the voltage controlled oscillator (VCO), the noise from the charge pump, the noise from the loop filter, and the noise in the reference clock. Some experiments are performed to verify the proposed theory. The curves of the theoretical upper bounds possess similar shapes with the experimental results.
In the second part, we derive state equations for linearized discrete-time models of CPPLLs from second-order loops to forth-order loops. We solve the differential equations of the loop filter by using the initial conditions and the boundary conditions in a period. The solved equations are linearized and rearranged as discrete-time state equations for checking stability conditions and overload conditions. Some behavioral simulations are performed to verify the proposed method. By examining the stability of loops with different conditions, we also propose an expression between the lower bound of the reference frequency, the open loop unit gain bandwidth, and the phase margin.
We hope that the analysis above is helpful to the engineers for designing charge-pump phase- locked loops.

誌謝………………………………………………………………………………I
摘要………………………………………………………………………………II
ABSTRACT………………………………………………………………………III
目錄………………………………………………………………………………V
圖錄……………………………………………………………………………VIII
表錄……………………………………………………………………………XII
符號說明………………………………………………………………………XIII

第一章 簡介………………………………………………………………………1
1.1研究動機………………………………………………………………………1
1.2文獻回顧………………………………………………………………………3
1.3 論文架構……………………………………………………………………4
第二章 充電泵鎖相迴路之基本理論……………………………………………5
2.1鎖相迴路的架構………………………………………………………………5
2.1.1 基本工作原理……………………………………………………………5
2.1.2 相位頻率偵測器…………………………………………………………7
2.1.3 充電泵及迴路濾波器……………………………………………………9
2.1.4 壓控震盪器……………………………………………………………10
2.1.5除頻器……………………………………………………………………11
2.2 鎖相迴路的數學模型……………………………………………………12
第三章 充電泵鎖相迴路連續時間模型之相位雜訊分析……………………15
3.1 各雜訊源的數學模型……………………………………………………16
3.2二階充電泵鎖相迴路連續時間模型之相位雜訊分析……………………21
3.3三階充電泵鎖相迴路連續時間模型之相位雜訊分析……………………27
3.4實驗結果與分析……………………………………………………………32
3.4.1 實驗設備………………………………………………………………32
3.4.2 二階充電泵鎖相迴路實驗結果………………………………………38
3.4.3三階充電泵鎖相迴路實驗結果…………………………………………40
第四章 充電泵鎖相迴路離散時間模型之穩定度分析………………………45
4.1 二階充電泵鎖相迴路離散時間模型之穩定度分析……………………48
4.2 三階充電泵鎖相迴路離散時間模型之穩定度分析……………………51
4.3 四階充電泵鎖相迴路離散時間模型之穩定度分析……………………58
4.4參考頻率與開迴路單位增益頻寬…………………………………………67
4.5 模擬結果…………………………………………………………………67
第五章 結論……………………………………………………………………82
附錄A：二階充電泵鎖相迴路連續時間模型輸出相位雜訊量測數據………84
附錄B：三階充電泵鎖相迴路連續時間模型輸出相位雜訊量測數據………87
附錄C：四階充電泵鎖相迴路變數重整推導過程……………………………90
附錄D：四階充電泵鎖相迴路變數代換列表.………………………………94
附錄E：四階充電泵鎖相迴路參考頻率與開迴路單位增益頻寬模擬參數…98
附錄F：三階充電泵鎖相迴路設計流程.……………………………………99
參考文獻………………………………………………………………………102

【1】 B. Razavi, “Challenges in design of frequency synthesizers for wireless applications,“ in Proc. IEEE 1997 custom integrated circuit conference, May 1997, pp. 395-402.
【2】 F. M. Gardner, “Charge-pump phase-lock loops,” IEEE Trans. Comm., vol. COM-28, no. 11, pp. 1849-1858, Nov. 1980.
【3】 W. O. Keese, “An analysis and performance evaluation of passive filter design technique for charge pump phase-locked loops,” National semiconductor Application Note 1001, May 1996.
【4】 K. Lim, S. H. Choi, and B. Kim, “Optimal loop bandwidth design for low noise PLL applications,” IEICE Trans. Fundamentals, vol. E80-A, pp. 1979-1985, Oct. 1997.
【5】 B. C. Sarkar and M. Nandi, “Additive noise response of a charge pump phase-locked loop,” IEICE Trans. Fundamentals, vol. E82-A, pp. 2291-2293, Oct. 1999.
【6】 Konstantin A. Douznetsov and Robert G. Meyer, “phase noise in LC Oscillators,” IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1244-1248, Aug. 2000.
【7】 B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 331-343, Mar. 1996.
【8】 M. Mansuri and C.-K. K. Yang, “Jitter optimization based on phase-locked loop design parameters,” IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1375-1382, Nov. 2002.
【9】 M. V. Paemel, “Analysis of a Charge-pump PLL: a New Model,” IEEE Trans. Comm., vol. 42, no. 7, pp. 2490-2498, July 1994.
【10】 P. K. Hanumolu, M. Brownlee, K. Mayaram, and Un-Ku Moon, “Analysis of charge pump phase locked loops,” IEEE Trans. Circuits Sys. I, vol. 51, no. 9, pp. 1665-1674, Sep. 2004.
【11】 D.H. Wolaver, phase-locked loop circuit design. Englewood Cliffs, NJ: Prentice Hall, 1991.
【12】 A. Hajimiri, “Noise in phase locked loops,” in Proc. 2001 Southwest Symp. Mixed-Signal Design, Feb. 2001, pp.1-6.
【13】 A. Mehrotra, “Noise analysis of phase-lock loops.” IEEE Trans. Circuits Syst. I, vol. 49, pp. 1309-1316, Sep. 2002.
【14】 Ali Hajimiri, Sotirios Limotyrakis, and Thomas H. Lee, “Jiter and Phase Noise in Ring Oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 179-194, June 1999.
【15】 Ali Hajimiri and Thomas H. Lee, “Oscillator Phase Noise,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 326-336, Mar. 2000.
【16】 Ayman ELsayed, Akber Ali, and M. I. Elmasry, “Differential PLL for Wireless Applications Using Differential CMOS LC-VCO and Differential Charge Pump,” in Proc. 1999 International Symposium on Low Power Electronics and Design, Aug, 1999, pp. 243-248.
【17】 Liang Dai and Ramesh Harjani, “Design of Low-Phase-Noise CMOS Ring Oscillators,” IEEE Trans. Circuits Syst. II, vol. 49, no. 5, pp. 328-338, May 2002.
【18】 Hamid R. Rategh and Thomas H. Lee, “A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver,” IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 780-787, May 2000.
【19】 A. A. Abidi, “High-frequency noise measurements on FET's with small dimensions,” IEEE Trans. Electron Devices, vol. ED-33, no.11, pp. 1081-1085, Nov. 1986.
【20】 D. B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of the IEEE, vol.54, no.2, pp. 329-330, Feb. 1966.
【21】 U. L. Rohde, Digital PLL Frequency Synthesizer. Englewood Cliffs, NJ: Prentice Hall, 1983.
【22】 S. Gradshteyn and I. M. Ryzhik, Table of integrals, series, and products. New York: Academic Press, 1980.
【23】 H. R. Rategh, H. Samavati, and T. H. Lee, “A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver,” IEEE J. Solid-State Circuits, vol.35, no.5, pp.780-787, May 2000.
【24】 W. -H. Chen ,G.-K. Dehng ,J.-W. Chen, and S.-I. Liu, “A CMOS 400-Mb/s serial link for AS-memory system using a PWM scheme,” IEEE J. Solid-State Circuits, vol.36, no. 10, pp.1498-1505, Oct. 2001.
【25】 R. S. Co and J. H. Mulligan, “Optimization of phase-locked loop performance in data recovery system,” IEEE J. Solid-State Circuits, vol.29, no. 9, pp. 1022-1034, Sep.1994.
【26】 P. Larrson, “A simulator core for charge-pump PLL's,” IEEE Trans. Circuits Syst. II, vol. 45, pp. 1323-1326, Sep. 1998.
【27】 P. Acco, M. P. Kennedy, C. Mria, B. Morley, and B. Frigyik, “Behavioral modeling of charge pump phase locked loops,” in Proc. IEEE Int. Symp. Circuits Syst., vol. 1, Orlando, FL, May 1999, pp. 375-378.
【28】 Charles L. Philips and H. Troy Nagle, Digital Control System Analysis and Design. Englewood Cliffs, NJ: Prentice Hall, 1995.
【29】 M. Vidyasagar, Nonlinear Systems Analysis. Englewood Cliffs. NJ: Prentice Hall, 1993.
【30】 劉深淵，楊清淵，「鎖相迴路」，滄海書局，台中，民國95年。
【31】 B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001.
【32】 R. E. Best, Phase-Locked Loops : Theory design and applications. New York: McGraw-Hill, 1984.
【33】 Chia-Yu Yao, Chin-Chih Yeh, and Chun-Te Hsu, “The Analysis of Phase-Jitter Variance for the Second-Order CPPLL Frequency Synthesizer,” in Proc. 2006 International Conference on Communications, Circuits and Systems, Guilin, China, June 2006, pp. 2503-2506.
【34】 Chia-Yu Yao, Chun-Te Hsu, and Chin-Chih Yeh, “The Analysis of Phase-Jitter Variance for the Third-Order CPPLL Frequency Synthesizer,”in Proc. 2006 IEEE Asia-Pacific Conf. Circuits Syst., Singapore, pp. 1043-1046, Dec. 2006.
【35】 Chia-Yu Yao, Chun-Te Hsu, and Chiang-Ju Chien, “Stability Analysis of Fourth-Order Charge-Pump PLLs Using Linearized Discrete-Time Models,” IEICE Trans. Electron., vol.E90-C, Mar. 2007.