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[1] R. Verma, “Flash memory quality and reliability issues,” Memory technology, Design and Testing, Records of the IEEE International Workshop on, pp. 32-36,Aug. 1996. [2] G. Campardo, R. Micheloni, D. Novosel, “VLSI-Design of Non-Volatile Memories,” Springer pp. 313-314, 2005 [3] K. Itoh, “VLSI Memory Chip Design,” Springer pp. 46-47, 2001. [4] 沈祐民 “Multilevel Sensing and Verifying Circuits for Flash Memory” 2004年碩士論文,中興大學。 [5] B. Ricco, G. Torelli, M. Lanzoni, A. Manstretta, H. E. Maes, D. Montanari, A. Modelli, “Nonvolatile multilevel memories for digital application,” Proceedings of the IEEE, vol. 8, no.12, pp.2399-2423, Dec. 1998. [6] C. Calligaro, A. Manstretta, A. Pierin and G Torelli,“Comparative Analysis of Sensing Schemes for Multilevel Non-Volatile Memories,” Proc. IEEE Int. Conf. on Innovative System in Silicon, pp. 266-273, Oct. 1997. [7] T. S. Jung, Y. J. Choi, K. D. Suh, “A 3.3V 128Mb Multi-Level NAND Flash Memory for Mass Storage Applications,” Solid-State Circuits Conference, Digest of Technical Papers. 43rd IEEE ISSCC96, 1996. [8] H. Nobukata, S. Takagi, K. Hiraga, “A 144-Mb, Eight-Level NAND Flash Memory with Optimized Pulsewidth Programming,” IEEE Journal of Solid-State Circuit, Vol. 35, no. 5, pp. 682-690, May. 2000.
[9] C. C. chung, H. Lin, Y. M. Shen, Y. T. Lin “A Multilevel Sensing and Program verifying Scheme for Bi-NAND Flash Memories,” IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, pp.267 -270, Apr. 2005. [10] H. Kurata, N. Kobayashi, K. Kimura, “A Selective Verify Scheme for Achieving a 5-MB/s Program Rate in 3-bit/cell Flash Memories,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 166-167, Jun. 2000. [11] T. N. Blalock, R. C. Jaeger, “A High-Speed Clamped Bit-Line Current-Mode Sense Amplifier,” IEEE Journal of Solid-State Circuit, Vol. 26, no. 4, pp. 542-548, Apr. 1991. [12] S. Sundaram, P. Elakkumanan, R. Sridhar, “High Speed Robust Current Sense Amplifier for Nanoscale Memories:- A Winner Take All approach,” International Conference on VLSI Design, Held jointly with 5th Internation Conference on Embedded Systems and Design, Jan. 2006. [13] C. C. Chung, H. Lin, Y. T. Lin, “A Novel High-Speed Sense Amplifier for Bi-NOR Flash Memories” IEEE Journal of Solid-State Circuits, Vol. 40, no. 2, pp. 515-522, Feb 2005. [14] P. Pavan, R. Bez, P. Olivo, E. Zanoni, “Flash Memory Cells-An Overview,” Proceedings of the IEEE, VOL. 85, no. 8, pp. 1248-1271, Aug 1997. [15] S. Gregori, A. Cabrini, O. Khouri, G. Torelli, “On-Chip Error Correcting Techniques for New-Generation Flash Memories,” Proceedings of the IEEE, Vol. 91, no. 4, pp. 602-616, Apr 2003.
[16] S. Gregori, O. Khouri, R. Micheloni, G. Torelli “An Error Control Code Scheme for Multilevel Flash Memories,” IEEE International Workshop on Memory Technology, Design and Testing, pp. 45-49, Aug. 2001. [17] C. k. Yuen, “The Separability of Gray Code,”IEEE Transactions on Information Theory, Vol. 20, no. 5, pp. 668, Sep 1974.
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