臺灣博碩士論文加值系統

近幾年來，由於半導體技術的進步及消費產品市場的趨勢，使得積體電路的設計朝向高速度與低功率發展，輸入/輸出介面在高速度與低功率的電路系統中扮演了極重要的角色。為了達到高速度與低功率的傳輸要求，數位系統可以使用低電壓差動輸出(low voltage differential signal, LVDS)標準所定義的傳輸方式來設計輸入輸出介面。故本論文之重點主要是介紹可以達到高速度與低功率之需求的LVDS傳送器與接收器之設計。另外也在此論文中介紹用來作為測試傳送器與接收器的鎖相迴路之設計。
在本篇論文中所設計之LVDS傳送器與接收器是以HSPICE來驗證電路，使用Cadence軟體來完成佈局，並以台積電之 3.3V 0.35um 1P4M CMOS製程來實現，其傳輸速度可達1Gb/s，電路操作的電源電壓範圍為1.8V~3.6V，操作在1.8V時的功率消耗為15mW，3.6V時的功率消耗為100mW，晶片大小為448um*481um，其中核心面積為240um*263um，傳送器為173um*78um，接收器為149um*41.5um。

In recent years, the advancement of fabrication and circuit design techniques as well as the trend of consumer products impels the integrated circuit designs toward high speed and low power applications. I/O interface plays an important role in achieving high speed and low power integrated circuit designs. Low voltage differential signal (LVDS) I/O standard used for data transmission between digital systems can fulfill the requirements of high speed and low power. In this thesis, the designs of transmitter and receiver for LVDS standard transceiver are investigated. A phase locked loop for testing the transceiver is also introduced.
HSPICE is used to verify functions of LVDS transmitter and receiver. Then the circuits are realized by using TSMC 0.35um 1P4M CMOS process provided by Chip Implementation Center (CIC). The chip can operate functionally at 1Gb/s under a power supply range from 1.8V to 3.6V. The power consumption is 15mW when operating at 1.8V and 100mW at 3.6V. The chip area is 448 x 481 m2, its core size is about 240 x 263 m2 including the transmitter size is 173 x 78 m2 and receiver is 149 x 41.5 m2.

Chinese Abstract.............................................Ⅰ
English Abstract.............................................Ⅱ
Acknowledgement..............................................Ⅲ
Contents.....................................................Ⅳ
Chapter 1 Introduction.......................................1
1.1 Movation.................................................1
1.2 Considerations of High Speed Circuit.....................3
1.2.1 Reflection...........................................3
1.2.2 Crosstalk............................................7
1.2.3 Ground Bounce........................................8
1.3 The LVDS Interface.......................................9
1.4 Thesis Organization......................................11
Chapter 2 Design of Transmitter..............................13
2.1 Introduction.............................................13
2.2 Circuit Design...........................................14
2.2.1 Circuit of transmitter...............................14
2.2.2 Termination of transmitter...........................15
2.2.3 Difference Amplifier.................................16
2.3 Simulation Results.......................................17
2.4 Summary..................................................22
Chapter 3 Design of Receiver.................................23
3.1 Introduction.............................................23
3.2 Circuit Design...........................................24
3.2.1 Parallel path op amp.................................24
3.2.2 The circuit of receiver..............................24
3.2.3 Termination of receiver..............................26
3.3 Simulation Results.......................................26
3.4 Summary..................................................29
Chapter 4 Design of Phase Locked Loop........................30
4.1 Introduction.............................................30
4.2 Circuit Design...........................................31
4.2.1 Phase Frequency Detector (PFD).......................31
4.2.2 Charge Pump..........................................33
4.2.3 Voltage Control Oscillator (VCO).....................35
4.2.4 Divider..............................................36
4.3 Simulation Results.......................................37
4.4 Summary..................................................43
Chapter 5 Measurement Results and Conclusion.................44
5.1 Measurement Results......................................44
5.2 Conclusion...............................................47
References...................................................49
Vita.........................................................51

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