臺灣博碩士論文加值系統

本文的目的是使用可規劃邏輯閘陣列(FPGA)來實現一個全數位式脈波寬度調變控制直流電壓轉換電路，建立控制系統的數學等效模型、電路特性及實現方式。
本文採用現成的類比到數位(ADC)積體電路(IC)元件來對輸出電壓取樣，而得到一個差值(Error)，此差值輸出到一個預先完成的「比例、積分、微分控制器(PID)」的查表控制電路中，進而得到一個脈波寬度調變的輸出結果。此脈波寬度調變輸出結果提供給一個四相位的降壓轉換器(Four-phase Buck converter)，來得到本文所要得到的電壓轉換結果。在全數位的控制電路當中，本文採用Verilog硬體描述語言(Verilog HDL)搭配Xilinx的ISE發展軟體及為希(ULINX)科技的FPGA硬體實驗板，來驗證本文的設計與性能。

The purpose of the thesis is to implement a fully digital pulse width modulation controlled DC to DC converter. This thesis is also aimed at building a mathematical effective module equal, circuit characterization and implementation to the fully digital pulse width modulation controlled DC to DC converter.
The thesis uses a ready ADC device to sample the input voltage and output an Error. The Error sends to a pre-calculated lookup-table PID controller and output a pulse width modulation result. After the result processed by a four-phase buck converter, we can get the voltage converting result of the thesis. Here we use Verilog HDL and Xilinx ISE develop environment under ULINX FPGA board to verify the design and performance in the thesis.

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表錄 viii
第一章 概論 -1-
1.1 研究背景 -1-
1.2 研究動機 -1-
1.3 交換式電源轉換器 -1-
第二章 數位脈波寬度調變控制器 -3-
2.1 控制電路 -3-
2.2 輸出電壓取樣電路 -5-
2.2.1 ADC0820 的操作模式 -5-
2.2.2 ADC0820 的工作原理 -6-
2.3 數位補償器電路 -7-
2.3.1 查表法 -8-
2.4 數位脈波寬度調變器 -9-
2.4.1 數位脈波寬度調變器的架構 -10-
第三章 數位控制器及系統模擬 -13-
3.1 數位控制器 -13-
3.1.1 離散系統穩定性分析 -13-
3.2 數位PID控制器參數設計 -14-
第四章 電路的實現 -18-
4.1 Verilog HDL -19-
4.2 A/D 轉換器 -20-
4.2.1 Verilog 描述A/D 轉換器控制信號 -22-
4.3 數位補償器 -24-
4.3.1 Verilog 描述數位補償器 -27-
4.4 數位脈波寬度調變器 -32-
4.4.1 Dead-time產生器 -35-
4.4.2 工作週期暫存器 -37-
4.4.3 Verilog 描述數位脈波寬度調變器 -38-
4.5 實驗結果 -47-
4.6 結論 -50-
參考文獻 -52-

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