臺灣博碩士論文加值系統

在數位積體電路中，CMOS元件已被廣泛應用，而CMOS IC 在電路中不可避
免的也會受到電磁干擾。電磁干擾的測試與分析可提供干擾防治對策，也
可提供積體電路設計的重要資訊，以達到電磁共容性設計。本篇論文主要
是研究電磁干擾對CMOS反及閘(NAND GATE)的影響，我們假設電磁干擾信
號耦合進入CMOS積體電路元件，以實驗研究此干擾對積體電路的影響，測
量電路對電磁干擾的感受度；並且以通用的軟體SPICE來模擬分析。我們
分析了干擾頻率和振幅對反及閘直流轉換曲線的影響，並探討分析預估模
式，來預估受電磁干擾後的直流轉換曲線變化。我們也分析了電磁干擾對
CMOS反及閘的上升與下降時間的影響。

CMOS devices are widely used in digital integrated circuits.
The opetation of these IC''s may be interfered by
electromagnetic interference ( EMI ) .EMI analyses and tests
can provide us the EMI emission and susceptibility information
of equipments.The analysis of conducted or radiated
interference is essential in the design of electromagnetic
compatibility (EMC)。 A study of effects of EMI on CMOS NAND
GATES is presented in this paper.Supposing an EMI signal has
been coupled into a terminal of the CMOS IC ,we have measured
and have simulated, with the aid of the general SPICE sofware,
the EMI susceptibility of CMOS NAND GATES . The DC
characteristics of CMOS NAND GATES under the interference of
different EMI frequencies and powers are analyzed. A method of
prediction the EMI effects on the DC transfer curve is
presented. Moreover,the rise time and fall time of CMOS NAND
GATES are also studied.