臺灣博碩士論文加值系統

本論文實現兩個連續漸近式類比數位轉換器。第一個是在0.18微米CMOS製程實現一個十二位元、每秒二千萬次取樣的連續漸進式類比數位轉換器；第二個是在55奈米低功耗CMOS製程實現一個十二位元、每秒六千萬次取樣的連續漸進式類比數位轉換器。為了避免使用大的電容值來滿足數位類比轉換電路的線性度要求，我提出兩個切換技術，分別是二元視窗切換以及電容交換技術，來解決線性度的問題。可以在不增加電容值情況下，提升整體類比數位轉換器的線性度，以滿足十二位元的精準度。
第一個晶片是在聯電的0.18微米製程實現，晶片面積為2.25平方毫米。其中，類比數位轉換器核心面積為0.1平方毫米。在1.5伏特供應電壓以及10MHz取樣頻率之下，他的功率消耗是1.17毫瓦。量測到的有效位元(ENOB)為9.3位元，主諧波比在使用電容交換技術之後可以達到86.6dB。對量測結果作分析與偵錯之後，它的改版晶片已在2017年六月下線。
第二個晶片是在聯電的55奈米低功耗CMOS製程實現。類比數位轉換器核心面積為156×230平方毫米。在1.2伏特供應電壓以及60MHz取樣頻率之下他的功率消耗是1.14毫瓦。後模擬得到的訊噪失真比為67.7dB，主諧波比為90dB。這個晶片已經在2017年五月下線。

This dissertation implements two successive-approximation registers (SAR) analog-to-digital converters (ADCs). The first is a 12-bit 20-MS/s SAR ADC in UMC 0.18µm CMOS. The second is a 12-bit 60-MS/s SAR ADC in UMC 55nm LPCMOS. In order to avoid large capacitance to meet the linearity requirement for DAC, we propose two switching techniques. There are the binary-window DAC switching technique and the capacitor-swapping technique to solve the problem of linearity.
The first SAR ADC was fabricated in UMC 0.18µm CMOS. The die area is 2.25mm2 and ADC uses a chip area of approximately 0.1mm2. The ADC consumes 1.17 mW from 1.5V supply voltage, and effective number of bit (ENOB) is 9.3 bits at 10 MS/s. The SFDR with capacitor swapping technique is 86.6dB. Though the analysis and results, the revised chip had been taped-out in June, 2017.
The second SAR ADC was fabricated in 55 nm LPCMOS and achieves 67.7 dB SNDR at 60 MS/s with only 1.14 mW of power consumption, leading to a FoM of 8.69 fJ/conversion-step and SFDR achieves 90dB. The ADC uses a chip area of approximately156×230 μm2. This chip had been taped-out in May, 2017.

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Target Specifications 2
1.3 Organization of the Thesis 3
Chapter 2 Background Survey 4
2.1 Background Introduction 4
2.2 Prior Works 5
2.2.1 Digital Calibration 5
2.2.2 Variable Window Technique 7
2.2.3 Two-Step Decision DAC Switching 9
2.2.4 Comparison of Prior ADC Architectures 11
Chapter 3 ADC Architecture 12
3.1 DAC Errors by the Capacitor Mismatch 13
3.2 Binary-Window DAC Switching 14
3.3 Capacitor Swapping [2] 18
3.4 Swapping Binary-Window DAC Switching 21
Chapter 4 A 12-bit 20-MS/s SAR ADC in 180nm CMOS 24
4.1 Sample and Hold Circuit 24
4.2 Comparator 30
4.3 Digital-to-Analog Converter 33
4.3.1 Capacitor Array Size Decision and Architecture 33
4.3.2 DAC Switching Scheme 34
4.4 SAR control logic 36
4.4.1 Self-Timed Loop 36
4.4.2 Binary-Window Controller 38
4.4.3 Encoder 38
4.5 Layout Consideration. 42
4.6 Post-Layout Simulation Results 44
4.7 Measurement Results 46
4.7.1 Measurement Environment 46
4.7.2 Experimental Results 48
4.8 Brief Summary 50
Chapter5 A 12-bit 60-MS/s SAR ADC in 55nm LP CMOS 51
5.1 Sample and Hold Circuit 51
5.2 Comparator 56
5.3 Digital-to-Analog Converter 59
5.3.1 Capacitor Array Decision and Its Architecture 59
5.3.2 DAC Switching Scheme 60
5.4 SAR Control Logic 62
5.4.1 Self-Time Loop 62
5.4.2 Binary-Window Controller 63
5.4.3 Encoder 63
5.5 Layout consideration 66
5.6 Post-Layout Simulation 68
5.7 Performance Summary 71
Chapter 6 Conclusions and Future Works 73
6.1 Conclusions 73
6.2 Future Works 74
Reference 75

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