臺灣博碩士論文加值系統

頻率合成器的主要功用是藉由輸入一個參考頻率，來產生一個或多個不同的輸出頻率。因此，常見於時脈產生器及收發器之中。有鑑於無線通訊系統的快速發展，及精確與穩定的高效能時脈需求，頻率合成器就顯得格外重要。
本論文提出一個全數位鎖相迴路之除小數型頻率合成器，其優點有二：一方面採具有控制性佳的全數位鎖相迴路為核心，一方面取具有精確度佳的除小數模式。我們設計一個新的相頻偵測器，來簡化傳統相頻偵測獨立的電路，以取代傳統的頻率與相位擷取模式獨立處理。根據改良的二元搜尋演算法，我們提出一個具有半階初始值的改良型相頻擷取模式，來加速頻率及相位的搜尋過程。並配合新的控制電路及線性度極佳的數位控制振盪器，來增加全數位鎖相迴路的穩定性。另外，使用具有除四與除五的雙模除頻器來實現除小數的目的，以增加頻率合成器的精確度。而整體電路的模擬結果也符合上述需求。
配合標準元件庫的數位設計流程，我們透過國科會晶片設計中心，以臺灣積體電路公司零點三五微米互補式金氧半導體製程下線製作。我們使用TimeMill及PowerMill工具驗證，整個晶片面積只有1.3 × 1.3 mm²，在輸出頻率為300MHz時，功率消耗只有15mW，抖動只有90ps，且鎖定時間在20個參考週期之內。

The frequency synthesizer is used to generate more one frequency from an input reference source for the applications of accuracy clock requirement, such as clock generator and transceiver. With the rapidly growth of wireless communication system and the high performance in clock accuracy and stability, the frequency synthesizer have became more important.
In this thesis, we proposed a fractional frequency synthesizer based on all digital phase-locked loop (ADPLL). A novel phase frequency detector (PFD) is developed for replacing the two independent detections of phase and frequency to improve the ADPLL performance. A modified phase frequency acquisition (PFA) is involved by the modified binary search algorithm (MBSA) with initial half-step size to speed up the convergence in both phase and frequency. The digital control oscillator (DCO) is investigated to have good linearity to further the ADPLL stability. And, the dual modulus frequency divider with divided by four or by five is applied to perform the variable fraction and to increase the accuracy of frequency synthesizer. Experimental results of overall simulation are well matched to our specification.
The frequency synthesizer is implemented to be a chip with TSMC 0.35μm 1p4m CMOS technology. The chip area is 1.3 x 1.3 mm². With the TimeMill and PowerMill tools, we got the more encourage simulation results. The power consumption is only 15mW, and the jitter is 90ps at 300MHz, and the locked time is less then 20 reference cycles.

摘要 iv
誌謝 vi
目次 vii
表目錄 ix
圖目錄 x
第一章 緒論 1
1.1 前言 1
1.2 研究動機 3
1.3 論文架構 4
第二章 頻率合成器的介紹 5
2.1直接類比頻率合成器 5
2.2直接數位頻率合成器 6
2.3 非直接（鎖相迴路）頻率合成器 7
2.3.1除整數型 8
2.3.2除小數型 9
2.4 全數位鎖相迴路 11
2.4.1基本架構及原理 11
2.4.2操作流程 13
2.4.3演算法 16
2.5 結論 19
第三章 全數位鎖相迴路之除小數頻率合成器之電路設計 21
3.1 架構及原理 21
3.2 數位控制振盪器 22
3.3 相頻偵測器 23
3.4 控制電路 25
3.4.1控制單元 25
3.4.2相頻增益暫存器 28
3.4.3加、減法器 30
3.4.4 Anchor暫存器 32
3.4.5數位控制振盪器控制位元暫存器 32
3.5 雙模除頻器 33
3.6 總結 34
第四章 晶片模擬結果 36
4.1 設計流程 36
4.2 模擬結果 36
4.2.1 數位控制振盪器 37
4.2.2 整個系統 39
4.3 晶片佈局 41
4.4 分析比較 43
第五章 結論與未來工作 46
5.1 結論 46
5.2 未來工作 46
參考文獻 47
附錄
A. 驗證說明（DRC 、LVS、PowerMill） 49

1. William F. Egan, Frequency Synthesis by Phase Lock, John Willey & Sons, Inc., 1999.
2. B. G. Glodberg, Digital Techniques in Frequency Synthesis, New York: McGRAW-Hill, 1996.
3. Terng-Yin Hsu, Chung-Cheng Wang and Chen-Yi Lee, "Design and Analysis of a Portable High-Speed Clock Generator," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 48, No. 4, Apr. 2001, pp. 367-375.
4. T. Olsson and P. Nilsson, "Fully integrated standard cell digital PLL," IEEE Electronics Letters, Vol.: 37, Feb. 2001, pp. 211-212.
5. Terng-Yin Hsu, Bai-Jue Shieh and Chen-Yi Lee, "An All-Digital Phase-Lock Loop(ADPLL) bsed Clock Recovery Circuit", IEEE Journal of Solid-State Circuits, Vol. 34, No. 8, Aug. 1999, pp. 1063-1073.
6. Sergei N. Bikkenin, David G.M. Cruickshank and Peter M. Grant, "Fractional-N Phase- Locked Loop for Frequency Synthesis," Phase Lock Loops: Theory and Practice (Ref. No. 1999/102), IEE Colloquium on, 1999, pp. 3/1-3/6.
7. A. Marques, M. Steyaert and W. Sansen, "Theory of PLL fractional-N frequency synthesizers," ACM Wireless Networks, Vol. 4, Jan. 1998, pp. 79-85.
8. Dejan Mijuskovic, Martin Bayer, Thecla Chomicz, Nitin Garg, Frederick James, Philip McEntarfer and Jeff Porter, “Cell-based fully integrated CMOS frequency synthesizer,” IEEE Journal of Solid-State Circuits, Vol. 29, Mar. 1994, pp. 271-279.
9. Dorin Emil Calbaza and Yvon Savaria, "Low-power direct digital frequency synthesis for wireless communications," IEEE Journal of Solid-State Circuits, Vol. 35, Mar. 2000, pp. 570-572.
10. Woogeun Rhee, Ali A. and Bang-Sup Song, "A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator," IEEE Journal of Solid-State Circuits, Vol. 35, No. 10, Oct. 2000, pp. 1453-1460.
11. Kuo-Hsing Cheng and Yu-Jung Chen, "A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency", ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International, 2001, pp. 139-143.
12. Duo Sheng, "An All Digital Phase-Locked Loop (ADPLL) with Fast Lock-In Time-- Analysis, Implementation and Application," Master Thesis, CCU, 1999.
13. Shyh-Jye Jou, Ya-Lan Tsao and I-YingYang, "An all digital phase-locked loop with modified binary search of frequency acquisition," Electronics, Circuits and Systems, 1998 IEEE International Conference on, Vol. 2, 1998, pp. 195-198.
14. Jim Dunny, Gerald Garcia, Jim Lundberg and Ed Nuckolls, "An All-Digital Phase- Locked Loop with 50-cycle Lock Time Suitable for High Performance Micro- processors," IEEE Journal of Solid-State Circuit, Vol. 30, No. 4, Apr. 1995, pp. 412-422.
15. Kuo-Hsing Cheng, Tse-Hua Yao, Shu-Yu Jiang and Wei-Bin Yang, “A difference detector PFD for low jitter PLL,” Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, Vol. 1, 2001, pp. 43-46.
16. Roland E. Best, Phase-Locked Loops, The McGraw-Hill Companies, Inc., 4th Edition, 1999.