臺灣博碩士論文加值系統

隨著高速有線傳輸的發展，通道損耗的議題也逐漸受到重視，而等化器(Equalizer)正是解決訊號失真的可行方案。本論文使用後遞式判別回授等化器(Decision Feedback Equalizer, DFE)做為主要架構，並以常模演算法(Constant Modulus Algorithm, CMA)完成權重的收斂，然而過去文獻大多以PC或FPGA等方式實現權重收斂演算法的設計，此舉降低了電路運作的方便性，有鑑於此，本論文以類比電路的方式將CMA實現於晶片內，由於其盲目等化器的架構，故本設計具有不需訓練序列即可套用於接收端的良好適應性。

本論文提出一應用於3.125 Gb/s Ethernet的基於常模演算法之後遞式判別回授等化器架構(CMA_DFE)，並以 TSMC 0.18 μm CMOS 製程實現，於1.8 V的工作電壓下，等化器電路的功率消耗為42mW，晶片面積為1.25 mm2。在後模擬中，此等化器可補償15公尺RG58A/U同軸電纜在Nyquist frequency 引起的12.23 dB損耗，誤碼率為5.6667e-5，在20公尺RG58A/U的16.75 dB損耗環境下，等化器則可將誤碼率由2.3871e-1降低為1.6633e-3，然而，對於以15公尺傳輸線實際量測等化器時誤碼率僅約為5e-2的情況，在本論文的最後也會進行原因的分析。

In high speed wireline communications, the frequency-dependent channel loss is an important issue. The equalizer is an effective method to resolve the frequency- dependent signal attenuation problem in wireline communications. This thesis realizes an on-chip constant-modulus-algorithm(CMA)-based decision feedback equalizer (DFE) to overcome the problem. The CMA is a blind equalization method, so it does not need a training sequence. Thus, the adaptive mechanism can be completely implemented on chip.
The wireline we consider in this thesis is the RG58A/U coaxial cable for 3.125 Gb/s Ethernet application. The CMA-based DFE chip was realized in TSMC 0.18 μm CMOS process. The equalizer consumed 42 mW power at 1.8 V supply. The chip area is 1.25 mm2. In post layout simulations, the proposed equalizer can compensate for a 12.23-dB channel loss at Nyquist frequency for a 15-meter RG58A/U cable with 5.6667e-5 BER. For a 20-meter RG58A/U cable with 16.75 dB loss at Nyquist frequency, the equalizer can improve the BER from 2.3871e-1 down to 1.6633e-3.

摘要 I
ABSTRACT II
誌謝 III
目錄 IV
圖目錄 VI
表目錄 IX
第一章 簡介 1
1.1 研究背景 1
1.2 研究動機 與目的 2
1.3 使用工具與模擬軟體 4
1.4 論文架構 4
第二章 等化器架構介紹 6
2.1 通道環境 6
2.2 等化器架構 8
2.2.1 Feed Forward Equalizer (FFE) 8
2.2.2 Decision Feedback Equalizer (DFE) 8
2.3 係數收斂演算法 10
2.3.1 Least Mean Square (LMS) 10
2.3.2 Constant Modulus Algorithm (CMA) 10
第三章 使用常模演算法的3.125 GB/S盲目後遞式判別回授等化器 13
3.1 CMA_DFE電路架構 13
3.2 Input buffer電路 15
3.3 Delay cell 電路 17
3.4 Combiner電路 21
3.5 Amplifier電路 22
3.6 CML DFE電路 23
3.7 DTS電路 24
3.8 Error estimator電路 25
3.9 Step controller電路 27
3.10 Gilbert cell電路 28
3.11 Integrator電路 31
3.12 Bias電路 32
3.13 Clk tuning電路 33
第四章 系統模擬及晶片量測結果 35
4.1 設計流程及晶片模擬結果 35
4.2 晶片佈局 40
4.3 晶片量測結果 42
4.3.1 量測環境 42
4.3.2 PCB電路板設計 43
4.3.3 量測結果 45
4.4 文獻比較 48
第五章 結論與未來展望 50
5.1 結論 50
5.2 未來展望 50
參考文獻 52

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