臺灣博碩士論文加值系統

本篇論文主要是針對結合離散餘弦轉換DCT (Discrete Cosine Transform)與離散小波轉換
DWT (Discrete Wavelet Transform) 設計一個可重組式的架構,利用最少的硬體實現這兩種轉換
法。DCT 在影像處理的規格上常見於JPEG、H.26X、MPEG1、2、4…等規格。而DWT 則因
為其具有多重解析以及可把訊號的頻帶做有效的分離,很適合用於影像的壓縮處理;目前常被
應用於JPEG2000 上。
在合併架構的處理上,我們修改蝴蝶結架構演算法的DCT 來縮小硬體需要量並增加其平行
度,同時提升DCT 的速度以便讓IP 的規格可以符合動態影像處理的需求。在DWT 的部分我們
選擇JPEG2000 標準中的9/7 filter 做為我們的設計目標,而為了與DCT的架構可以做結合,我們
捨棄了最小硬體設計的提升式演算法 (Lifting scheme),改以迴旋積分 (convolution based)的演
算法來處理。
由於DCT 與DWT 的乘法係數都為定數,因此在硬體設計上我們針對乘法的部分採用
canonic signed digit (CSD) encoded multiplier 來取代傳統的乘法器的設計,並且再有效利用DCT
與DWT 間的係數關係,來設計一個可變式定數乘法器 (VCM ,variable constant multiplier),以期
達到降低面積上的需求,而且以CSD encoded multiplier 的設計亦可幫助我們提升此IC 的速度。
在硬體實現方面,我們利用硬體描述語言 (Verilog Hardware Description Language)來設計此
架構,並在台積電所提供的.13 製程library 及Synopsys 所提供的合成軟體做合成電路,而本篇所
提的電路最高時脈可達105MNz,而面積為11940gate counts。與近期發表的ASIC 的 DCT 加
DWT 架構相比,我們的設計大約可省33%的面積,並在速度亦可符合MPEG2 的規格。

This paper presents a design and development of a reconfigurable architecture for image
transform coding. Because of DCT (Discrete Cosine Transform) is usually used in JPEG,
MPEG, and H.26X system. And DWT (Discrete Wavelet Transform) is used in JPEG2000
system. They are both the part that damage huge computations in system. So we want to
integrate DCT and DWT architectures with the same hardware to reduce hardware
requirement for these system.
To merge DWT into DCT, we use butterfly structure for DCT and 9/7 convolution based
structure for DWT that not only can make DCT computations time faster, but also can
increase hardware utility rate for DWT.
To reduce hardware area and speed up DCT function, we use the subexpression to reduce
our hardware requirement and canonic signed digit (CSD) encoded multiplier to design ours
multiplication that can effective reduce multiplication area, and also can speed up the chip to
achieve the mpeg spec.
The architecture executes a DCT and DWT achieving up to 90% higher throughput and
occupying as little as 20% area compared to a commercial digital signal processing and other
application- specified integrated circuit implementations while maintaining precision. A
comprehensive comparative analysis is also provided. The proposed architecture is
implemented in 0.13- m CMOS technology and operates with a 100-MHz clock.

中文摘要 ……………………………………………………………… i
英文摘要 …………………………………………………………… ii
誌謝 ………………………………………………………………… iii
目錄 ………………………………………………………………… iv
表目錄 ……………………………………………………………… vi
圖目錄 ……………………………………………………………… vii
一、 序論……………………………………………………………… 1
1.1 動機………………………………………………………………… 1
1.2 影像資料壓縮簡介………………………………………………… 2
1.3 我們的設計………………………………………………………… 2
1.4 章節介紹…………………………………………………………… 3
二、 背景知識與相關研究…………………………………………… 4
2.1 多媒體系統簡介 ………………………………………………… 4
2.2 離散餘弦(DCT)轉換演算法……………………………………… 7
2.2.1 DCT(離散餘弦轉換)與影像處理介紹………………………… 7
2.2.2 量化效應…………………………………………………………7
2.2.3 一維DCT演算法………………………………………………… 8
2.2.4 二維DCT架構分析……………………………………………… 10
2.2.5 DCT硬體架構……………………………………………………10
2.3 離散小波轉換…………………………………………………… 12
2.3.1 離散小波轉換(DWT)與影像壓縮……………………………… 12
2.3.2 離散小波轉換硬體實現方式………………………………… 13
2.3.3 Daubechies 9/7 Convolution-Based 濾波器…………… 13
2.3.4 Daubechies 9/7 Lifting-Based 濾波器…………………… 15
2.4 相關研究………………………………………………………… 18
三、 DCT 與DWT 可重組架構設計…………………………………… 26
3.1 DCT 架構設計與分析…………………………………………… 26
3.1.1 DCT 偶函數架構設計與分析………………………………… 27
3.1.2 DCT 奇函數架構設計與分析………………………………… 29
3.1.3 DCT 係數乘法器設計………………………………………… 32
3.2 DWT 架構設計與分析…………………………………………… 36
3.2.1 9/7 Daubechies 濾波器架構設計…………………………… 37
3.2.2 9/7 Daubechies 濾波係數乘法器設計……………………… 38
3.3 效能評估………………………………………………………… 45
四、 實驗結果與討論……………………………………………… 46
4.1 模擬與驗證環境……………………………………………… 46
4.2 實驗結果與分析討論………………………………………… 47
4.2.1 Real time constraint 的比較…………………………… 47
iv
4.2.2 與相關研究效能比較……………………………………… 48
4.2.3 與AISC IC 效能比較……………………………………… 49
五、 結論與未來工作……………………………………………… 50
參考文獻 …………………………………………………………… 51

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