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研究生:陳俊佑
研究生(外文):Chun Yu Chen
論文名稱:奈米線電晶體的微縮特性之研究
論文名稱(外文):Study on Scaling Capability of Nanowire Transistors
指導教授:江孟學,鄭岫盈
指導教授(外文):Meng-Hsueh Chiang,Shiou-Ying Cheng
學位類別:碩士
校院名稱:國立宜蘭大學
系所名稱:電子工程學系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:105
中文關鍵詞:奈米線量子物理模型微縮特性
外文關鍵詞:nanowirequantum mechanical modelscaling
相關次數:
  • 被引用被引用:2
  • 點閱點閱:315
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  • 下載下載:35
  • 收藏至我的研究室書目清單書目收藏:0
本論文主要研究奈米線電晶體的微縮特性之研究,透過學理分析與三維數值模擬,深入探討奈米線電晶體、鰭式電晶體與三閘極電晶體通道微縮能力,以及對抗短通道效應的能力。從量子物理模型的選擇開始,因微影製程快速進步,量子效應在近幾年備受重視,為了深入了解基本的物理意義,選用量子物理模型預測將是微縮特性研究前的準備。進一步我們與古典物理模型互相驗證,包含矽薄膜厚度與製程變異性對奈米線元件的影響,再利用三維電子切面圖驗證其正確性。選擇了考量的量子物理模型,切入電晶體微縮特性比較的主體,由奈米線電晶體、鰭式電晶體與三閘極電晶體三者在量子物理模型考量下進行通道微縮的比較,從製程角度出發分析不同矽薄膜厚度、製程變異性與通道微縮之影響。模擬結果顯示出奈米線元件除了具抵抗矽薄膜厚度的影響外,還具有製程的可塑性,更有通道微縮的潛能。並且與傳統MOSFET的設計考量進行比較,發現奈米線元件與傳統MOSFET規則不同。
以實現電路設計操作速度上的效能比較,本論文以CV/Ion作為先進元件的操作速度特性比較基礎,結果顯示鰭式電晶體在電路應用上有較快的操作速度,考量製程變異性時奈米線元件在矽薄膜特性表現比較穩定,並進一步對奈米線元件作最佳化矽薄膜厚度的設計。最後驗證在晶圓與通道方向不同使特性改變,奈米線元件在不同通道方向時能具有穩定的效能,對於積體電路而言,採用高穩定度的奈米線元件會是非常適合的選擇。
The thesis mainly focuses on the scaling capability of the nanowire transistors, and the impact of quantum effect is investigated via physical 3D numerical simulation. We analyze the channel scalability and discuss how to control the short channel effects of nanowire, FinFET and Tri-Gate transistors characteristics. Several emerging patterning processes have been proposed in recent years. Due to device size scaling, quantum mechanical effects become significant. The physical quantum mechanical model is one of key figures for 3D numerical device simulation. The quantum mechanical model is analytically studied and compared with classical model. The characteristics of electron distributions on different surface orientations subject to film thickness and manufacturability of the nanowire device are investigated via 3D numerical simulation. We comprehensively examine the three types of multiple-gate structures including nanowire, FinFET and Tri-Gate devices.
In order to evaluate the device performance when considering speed for logic application, the thesis also focuses on CV/Ion for CMOS inverter with advanced multiple-gate devices.
致謝 I
摘要 II
Abstract III
目錄 IV
圖目錄 VI
表目錄 XV
Chapter 1 序論 1
1 - 1. 前言 1
1 - 1 - 1. 多閘極元件 1
1 - 1 - 2. 短通道效應 2
1 - 1 - 3. 量子效應 2
1 - 2. 研究動機 3
1 - 3. 章節架構 3
Chapter 2 量子效應對奈米線的影響 5
2 - 1. 量子物理模型(M.L.D.A.)對奈米線的影響 5
2 - 1 - 1. 半導體方程式簡介 5
2 - 1 - 2. M.L.D.A.模型之簡介 6
2 - 1 - 3. 模擬元件結構介紹 7
2 - 1 - 4. M.L.D.A.模擬分析 7
2 - 2. 量子物理模形 ( D.G. ) 對奈米線的影響 11
2 - 2 - 1. D.G.模型之簡介 11
2 - 2 - 2. D.G.模擬分析 12
2 - 3. 無量子效應時的奈米線元件特性比較 14
2 - 3 - 1. 電氣特性比較 15
2 - 3 - 2. 不同半徑下的電子分佈比較 18
2 - 3 - 3. 製程變異性電子分佈比較 31
Chapter 3 奈米線元件與多閘極元件的微縮能力 42
3 - 1 - 1. 奈米線元件的微縮能力 42
3 - 1 - 2. 鰭式電晶體的微縮能力 46
3 - 1 - 3. 三閘極電晶體的微縮能力 50
3 - 1 - 4. 先進元件通道微縮模擬結果的比較 54
3 - 1 - 5. 奈米線元件與傳統MOSFET設計考量比較 57
Chapter 4 奈米線元件的效能比較 63
4 - 1. 多閘極元件的電容特性比較 63
4 - 2. 奈米線場效應電晶體元件的最佳化 66
4 - 3. 先進元件通道方向不同對元件影響 74
4 - 3 - 1. 研究模型建立 74
4 - 3 - 2. 模擬結果與比較 76
Chapter 5 結論 85
參考文獻 86
[1]施敏原著,黃調元譯, “半導體元件物理與製程技術 (第二版),” 國立交通大學出版社, 2002.
[2]Michael Quirk與Julian Serda著, 劉文超與許渭州校閱, 羅文雄、蔡榮輝與鄭岫盈譯, “半導體製程技術,” 台灣培生教育出版股份有限公司, 2004.
[3]S. Deleonibus, “Physical and technological lomitations of NanoCMOS device to the end of the roadmap and beyond,” Eur. Phys. J. Appl. Phys. , Jan. 2007, pp. 197-214
[4]Leland Chang, Yang-Kyu Choi, Jakub Kedzierski, Nick Lindert, Peiqi Xuan, Jeffery Bokor, Chenming Hu, and Tsu-Jae King, “Moore’s Law Lives On,” IEEE CIRCUITS & DEVICE, Jan. 2003, pp. 35-42.
[5]P.M. Solomon, K.W. Guarini, Y. Zhang, K.K. Chan, E.C. Jones, G.M. Cohen, A.Krasnoperova, Maria Ronay, O. Dokumaci, H.J. Hovel, J.J. Bucchignano, C. Cabral Jr., C. Lavoie, V. Ku, D.C. Boyd, K.S. Petrarca, J.H. Yoon, I.V. Babich, J. Treichler, P.M. Kozlowski, J.S. Newbury, C.P. D’Emic, R.M. Sicina, J. Benedict, and H.-S.P. Wong, “Two Gate Are Better Than One,” IEEE CIRCUITS & DEVICE, Jan. 2003, pp. 48-62.
[6]Taurus Process & Device User Manual Version X, Feb. 2005.
[7]D. J. Frank, S. E. Laux and M. V. Fischetti, “Monte Carlo Simulation of a 30nm Dual-Gate MOSFET: How Short Can Si Go?,” IEEE IEDM, Dec. 1992, pp. 553-556.
[8]Xiaoping Liang, and Yuan Taur, “A 2-D Analytical Solution for SCEs in DG MOSFETs,” IEEE Trans. Electron Devices, vol. 51, no. 8, Aug. 2004, pp. 1385-1391.
[9]Leland Chang, Stephen Tang, Tsu-Jae King, Jeffrey Bokor and Chenming Hu, “Gate Length Scaling and Threshold Voltage Control of Double-Gate MOSFETs.” IEEE IEDM, Dec. 2000, pp. 719-722.
[10]Yuan Taur, “An Analytical Solution to a Double-Gate MOSFET with Undoped Body,” IEEE CIRCUIT & DEVICE, vol. 21, no. 5, May. 2000, pp. 245-247.
[11]Huaxin Lu and Yuan Taur, “An Analytical Potential Model for Symmetric and Asymmetric DG MOSFET,” IEEE Trans. Electron Devices, vol. 53, no. 5, May. 2006, pp. 1161-1168.
[12]Jerry G. Fossum, Lixin Ge, and Meng-Hsueh Chiang, “Speed Superiority of Scaled Double-Gate CMOS,” IEEE Trans. Electron Devices, vol. 49, no. 5, May. 2002, pp. 808-811.
[13]Yuan Taur, “Analytical Solutions of Charge and Capacitance in Symmetric and Asymmetric Double-Gate MOSFETs,” IEEE Trans. Electron Devices, vol. 48, no. 12, Dec. 2001, pp. 2861-2869.
[14]Gianluca Fiori and Giuseppe Iannaccone, “Three-Diamensional Simulation of One-Dimensional Transport in Silicon Nanowire Transisors,” IEEE Trans. Electron Devices, vol. 6, no. 5, Sept. 2007, pp. 524-529.
[15]M. Bescond, K. Nehari, J.L. Autran, N. Cavassilas, D. Munteanu, and M. Lannoo, “3D Quantum Modeling and Simulation of Multiple-Gate Nanowire MOSFETs,” IEEE IEDM, Dec. 2004, pp. 617-620.
[16]E. Gnani, S. Reggiani, M. Rudan, G. Baccarani, “A Quantum-Mechanical Analysis of the Electrostatics in Multi-Gate FETs,” IEEE SISPAD, Sept. 2005, pp. 291-294.
[17]Ramesh Venugopal, Zhibin Ren, and Mark S. Lundstrom, “Simulating Quantum Transport in Nanoscale MOSFETs: Ballistic Hole Tansport, Subband Engineering and Boundary Conditions,” IEEE Trans. Electron Devices, vol. 2, no. 3, Sept. 2003, pp. 135-143.
[18]G. Paasch and H. Übensee, “A Modified Local Density Approximation: Electron Density in Inversion Layers,” Phys. Stat., May. 1982, pp. 165-178
[19]International Technology Roadmap for Semiconductors, 2006. Online: http://public.itrs.net/.
[20]Ji-Woon Yang and Jerry G. Fossum, “On the Feasibility of Nanoscale Triple-Gate CMOS Transistors,” IEEE Trans. Electron Devices, vol. 52, no. 6, June. 2005, pp. 1159-1164.
[21]Wei Bian, Jin He, Yu Chen, Yue Fu, Rui Zhang, Lining Zhamg, and Mansun Chan, “Complicated Subthreshold Behavior of Undoped Cylindrical Surrounding-Gate MOSFETs,” IEEE EDSSC, Dec. 2007, pp. 589-592.
[22]Hamdy Abd El Hamid, Benjamin Iñíguez, and Jaume Roig Guitart, “Analytical Model of the Threshold Voltage and Subthreshold Swing of Undoped Cylindrical Gate-All-Around-Based MOSFETs,” IEEE Trans. Electron Devices, vol. 54, no. 3, Mar. 2007, pp. 572-578.
[23]Andreas Wettstein, Andreas Schenk, and Wolfgang Fichtner, “Quantum Device-Simulation with the Density-Gradient Model on Unstructured Grids,” IEEE Trans. Electron Devices, vol. 48, no. 2, Feb. 2001, pp. 279-284.
[24]Fu-Liang Yang, Di-Hong Lee, Hou-Yu Chen, Chang-Yun Chang, Sheng-Da Liu, Cheng-Chuan Huang, Tang-Xuan Chung, Hung-Wei Chen, Chien-Chao Huang, Yi-Hsuan Liu, Chung-Chen Wu, Chi-Chun Chen, Shih-Chang Chen, Ying-Tsung Chen, Ying-Ho Chen, Chih-Jian Chen, Bor-Wen Chan, Peng-Fu Hsu, Jyu-Horng Shieh, Han-Jan Tao, Yee-Chia Yeo, Yiming Li, Jam-Wem Lee, Pu Chen, Mong-Song Liang, and Chenming Hu., “5nm-Gate Nanowire FinFET,” IEEE VLSI Digest of Technical Papers, June 2004, pp. 196-197.
[25]Bipul C. Paul, Shinobu Fujita, and Masaki Qkajima, “Impact of a Process Variation on Nanowire and Nanotube Device Performance,” IEEE Trans. Electron Devices, vol. 54, no. 9, Sept. 2007, pp. 2369-2376.
[26]Yiming Li, Hung-Mu Chou, and Jam-Wem Lee “Investigation of Electrical Characteristics on Surrounding-Gate and Omega-Shaped-Gate Nanowire FinFETs,” IEEE Trans. Electron Devices, vol. 4, no. 5, Sept. 2005, pp. 510-516.
[27]M.H. Na, E.J. Nowak, W. Haensch, and J. Cai, “The Effective Drive Current in CMOS Inverters,” IEEE IEDM, Dec. 2002, pp. 121-124.
[28]Leland Chang, MeiKei Ieong, and Min Yang“CMOS Circuit Performance Enhancement by Surface Orientation Optimization,” IEEE Transactions on Electron Devices, Vol. 51, NO. 10, Oct. 2004, pp. 1621-1627.
[29]F. Schäfler, “High-mobility Si and Ge structures,” Semiconductor Science and Technology, vol. 12, Dec. 1997, pp. 1515-1549.
[30]Masaharu kobayashi and Toshiro Hiramoto, “Experimental study on quantum confinement effects in silicon nanowire metal-oxide-semiconductor field-effect transistors and single-electron transistors,” J. Appl. Phys. 103, 053709 (2008).
[31]Yuan Taur and Tak H. Ning, 1998, Fundamentals of Mooern VLSI Devices, New York.
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