臺灣博碩士論文加值系統

近年來，消費者對行動及穿戴裝置的需求逐漸成長，電子產品朝向更輕、薄、短、小的設計趨勢也愈加明顯。影像感測器模組在行動及穿戴裝置中是一個關鍵零組件，影像感測器模組的尺寸大小也會直接影響電子產品的體積。因此，如何設計一個輕、薄、短、小的影像感測器模組變成一個重要課題，愈來愈多的研發資源也投入到相關領域。其中，縮小感光像素的尺寸是一個有效的方法來縮小影像感測器模組的體積。然而，此方法所要付出的代價是較差的動能範圍、較少的光電子儲存能力及較低的靈敏度。在本論文中，我們提出三種新技術來解決以上問題。
首先，一個利用二次曝光(長、短曝光)、單次讀取技術的寬動態範圍互補式金氧半導體影像感測器被提出。此影像感測器可達成行平行高低照度像素的偵測。並藉由此功能，可選擇性的讀取長曝光訊號(低照度像素)或短曝光訊號(高照度像素)並加以數位化。此「高低照度像素偵測」的功能己被整合在所提出的行平行類比數位轉換器中，因此每一個像素在讀取時，首先會執行高低照度像素的偵測，並根據偵測結果來讀取長曝光訊號或短曝光訊號，最終再合成一幅寬動態範圍的影像。相較於傳統的二次曝光或多次曝光技術，此方法可減少系統所需的記憶體容量及類比數位轉換器的執行次數，因此耗電可大幅降低。另外，此影像感測器動態範圍的大小可藉由調整長、短曝光時間的比例來加以控制。
另外，所提出的行類比數位轉換器還有另外一種操作模式，光電子儲存能力延展模式。此操作模式可解決傳統的四電晶體主動式像素感測器因像素尺寸微縮所造成光電子儲存能力降低的問題。傳統的四電晶體主動式像素感測器只將光電子儲存在光電二極體中，而在所提出的方法中，除了將光電子儲存在光電二極體中，一旦光電二極體所儲存的光電子達到了上限，多餘的光電子會溢位並儲存在浮動擴散層中，因此也增加了四電晶體主動式像素感測器的光電子儲存能力。所
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提出的行平行類比數位轉換器具有判斷是否有溢位的光電子儲存在浮動擴散層中的功能，並可累加儲存在光電二極體和浮動擴散層中的光電子。可減少行類比數位轉換器的執行次數並降低耗電。
最後，本論文提出一個內建自我測試功能的三維整合影像感測器層來縮小晶片面積。較小的晶片面積可有效縮小影像感測器模組的體積。所提出的三維整合影像感測器層是由許多的子像素陣列所組成，每個子像素陣列各自獨立且可平行運作。當子像素陣列的數目增加，影像感測器的解析度也變高，但影像感測器的畫面更新率卻可維持不變，這是此架構的最大優點。除此之外，所提出的內建自我測試電路可以在晶片堆疊前，偵測出不合格的晶片，以提升晶片堆疊後的良率。所提出的內建自我測試電路並不會增加像素電路的複雜度，因此整體影像感測器對光強度的靈敏度並不會因此下降。所提出的三維整合影像感測器層非常適合使用在需小影像感測器模組的應用上。

The fast growing demand of thin and compact mobile and wearable devices has driven the efforts to reduce the size of camera module. CMOS image sensor (CIS) with small pixel dimension is an effective solution to implement a small size camera module. The design challenges of CMOS image sensor with small pixel dimension are low dynamic range, low full well capacity (FWC) and low sensitivity. In this thesis, three new techniques are proposed to address the problems.
Firstly, a dual-exposure single-capture wide dynamic range CMOS image sensor for mobile devices is proposed. The proposed sensor achieves column-wise highly/lowly-illuminated pixel detection, and only the “adequate” voltage signal (long- or short-exposure signal) is digitized. With an integrated highly/lowly-illuminated pixel detection function in the column-wise single slope ADC, each pixel is read out only once with highly- or lowly-illuminated pixel index for synthesis of a wide DR frame. This approach can dramatically reduce the power dissipation compared to existing multi-frame-readout solutions. The dynamic range expansion ratio is programmable, and depends on the time ratio of long-exposure to short-exposure period.
Secondly, a novel single-slope ADC design and operation is proposed to expand full well capacity of CMOS image sensor with small pixel dimension. With the proposed technique, charges stored in the photodiode and floating diffusion of 4T active pixel sensor are all read out and accumulated by the proposed SS ADC to improve the FWC. Only one A/D conversion is required for each pixel, which decreases chip power consumption compared to the general double A/D conversion operation.
Finally, because 3D IC is an emerging solution to reduce chip size, a 3D-integrated
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CMOS image sensor layer with built-in self-test function for 3-layer stacking CMOS imager is proposed. A modular CIS sub-array is proposed with new readout and control scheme. The proposed readout structure with in-pixel two-dimensional (2D) decoding function achieves high spatial resolution, without degrading the frame rate. A BIST circuit is also proposed to filter out unqualified CIS layer before chip stacking, improving the yield performance of the final 3D integrated imagers, without adding extra transistor in the pixel. The proposed 3D-integrated CIS layer is very suitable for small size camera module applications.

CONTENTS
摘要 I
ABSTARCT III
致謝 V
CONTENTS VI
LIST OF FIGURES IX
LIST OF TABLES XIII
CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 RESEARCH GOALS AND CONTRIBUTION 4
1.3 THESIS ORGANIZATION 5
CHAPTER 2 BACKGROUND 7
2.1 PIXEL STRUCTURE 7
2.1.1 Passive Pixel Sensors (PPS) 7
2.1.2 3T-Active Pixel Sensors 9
2.1.3 4T-Active Pixel Sensors 10
2.1.4 Back-Side Illumination Sensor (BSI) 13
2.2 READOUT ARCHITECTURES OF CMOS IMAGE SENSORS 14
2.3 PIXEL READOUT SCHEME 16
2.3.1 Rolling Shutter 16
2.3.2 Global Shutter 18
2.4 WIDE DYNAMIC RANGE TECHNIQUES 20
2.4.1 Logarithmic Sensor 20
2.4.2 Linear-logarithmic Sensor 21
2.4.3 Lateral Overflow Integration Capacitor (LOFIC) 22
2.4.4 Dual-exposure 24
2.4.5 Multiple-exposure 26
2.5 3D-INTEGRATED CMOS IMAGE SENSOR 28
2.6 SUMMARY 30
CHAPTER 3 WIDE DYNAMIC RANGE CMOS IMAGE SENSOR 31
3.1 INTRODUCTION 31
3.2 PROPOSED WIDE DR CMOS IMAGE SENSOR 33
3.2.1 Readout Flow 33
3.2.2 Pixel Operation 34
3.2.3 Proposed Single-Slope ADC 37
3.2.4 Photoelectric Conversion Curve Analysis 41
3.3 EXPERIMENTAL RESULTS 43
3.4 CONCLUSION 50
CHAPTER 4 FULL WELL CAPACITY EXPANSION TECHNIQUE 51
4.1 INTRODUCTION 51
4.2 FULL WELL CAPACITY EXPANSION MODE 53
4.2.1 Main Idea 53
4.2.2 Single-Slope ADC Design and Operation 57
4.3 EXPERIMENTAL RESULTS 61
4.4 CONCLUSION 65
CHAPTER 5 3D-INTEGRATED CMOS IMAGE SENSOR 66
5.1 INTRODUCTION 66
5.2 CIS LAYER DESIGN 69
5.2.1 Conventional 2D CMOS Imager Architecture 69
5.2.2 Proposed 3D CIS Layer Architecture 70
5.2.3 4-Shared Pixel Circuit 71
5.2.4 Pixel Operation in Normal Mode 73
5.2.5 Pixel Operation in Self Test Mode 77
5.2.6 Pixel Layout 78
5.3 BIST 79
5.3.1 Pixel Defect Modes 79
5.3.2 Design Considerations 80
5.3.3 Self Test Flow 81
5.3.4 BIST Circuit 82
5.3.5 Comparator 84
5.4 MEASUREMENT RESULTS 85
5.5 CONCLUSION 92
CHAPTER 6 CONCLUSION AND FUTURE WORKS 94
6.1 CONCLUSION 94
6.2 FUTURE WORKS 95
BIBLIOGRAPHY 97

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