臺灣博碩士論文加值系統

本論文中，所運用到的元件是屬於操作在高壓條件下，N 型金屬-氧化物-半導體場效電晶體，元件本身是空乏型的所以臨限電壓很低甚至接近零伏特。而我們將探討的是電晶體當中因閘極端引發汲極端漏電流而導致元件本身在尚未導通之前產生的崩潰效應。

實驗過程中，為了最佳化元件本身的特性。我們發現崩潰電壓本身與汲極、源極參雜濃度並非線性增加的關係，反到呈現鐘型分佈的形狀，也就是關係式中有一個最佳化條件。在這樣一個相對應的關係式中，我們可以藉由兩種截然不同的機制來詮釋。其中一項崩潰機制是落在鐘型分佈的左半區間，其中最大電場主要是發生在閘極的邊緣。反觀另外一種崩潰機制，也就是鐘型分佈的右半區間，電場則是集中在汲極與基極端的接面處。

然而我們可以藉由實驗的結果以及論點來解釋崩潰電壓與摻雜濃度、摻雜能量之間的關聯性。此外，實驗當中我們也可清楚了解崩潰電壓會因製程條件的變化而有明顯差異，文中也會針對過蝕刻造成矽基板損耗而影響崩潰電壓的論點提出證明。最後結論我們認為崩潰電壓的改善以及矽基板損
耗所造成製程中不穩定的因素都是可以藉由實驗結果被有效控制的。

A gate-induced-drain-leakage-induced OFF-state breakdown is examined in our high-voltage depletion-mode n-channel metal–oxide–semiconductor
field-effect transistors.

By increasing the dosage in the n-region, a bell-shaped trend between the OFF-state breakdown voltage VBD and the dosage in the n-region is observed.Such a bell-shaped trend is found to result from two competing factors: an electric field in the gate edge and an electric field associated with the drain–bulk junction. The latter electric field is responsible for the falling part in the bell-shaped trend. Our model can explain the data of the slightly bell-shaped
trend between OFF-state VBD and implant energy in the n-region.

Additionally, the effect of Si recess variation on OFF-state VBD variation can be understood from our model. According to our model, approaches to improve OFF-state VBD and the effect of Si recess variation on VBD variation are proposed.

Base on the thesis results, no mater the improvement of off state breakdown or the impact of process variation all can be controlled in our experiment results.

目錄　　　　　　
中文提要 …………………………………………………………… i
英文提要 …………………………………………………………… ii
誌謝 …………………………………………………………… iii
目錄 …………………………………………………………… iv
表目錄 …………………………………………………………… vi
圖目錄 …………………………………………………………… vii
第一章、 緒論……………………………………………………………………………1
1.1 研究背景與動機………………………………………………………2
1.2 論文的編制………………………………………………………………3
第二章、 實驗元件與實驗量測介紹………………………………………5
2.1 元件結構……………………………………………………………………5
2.1.1 元件參數特性……………………………………………………………6
2.2 實驗規劃……………………………………………………………………7
2.2.1 實驗裝置……………………………………………………………………7
2.2.2 實驗理論……………………………………………………………………8
2.2.3 結論……………………………………………………………………………8
第三章、 外加偏壓與元件崩潰效應之關聯…………………………13
3.1 元件崩潰機制……………………………………………………………13
3.1.1 Punch Through 汲極到源極漏電流………………13
3.1.2 Junction Breakdown 接面崩潰…………………14
3.1.3 GIDL閘極引發汲極漏電……………………………………… 15
第四章、 元件崩潰電壓改善之研究…………………………………… 21
4.1 實驗動機………………………………………………………………… 21
4.2 閘極到汲極接點距離對崩潰電壓之影響……………21
4.2.1 實驗機制探討………………………………………………………… 21
4.2.2 結果與討論………………………………………………………………23
4.3 元件參雜濃度與能量對崩潰電壓之影響……………23
4.3.1 實驗機制探討………………………………………23
4.3.2 結果與討論……………………………………………26
4.4 多重摻雜對元件結構影響之影響……………………… …26
4.4.1 實驗動機………………………………………………26
4.4.2 結果與討論……………………………………………27
第五章、 製程變異影響崩潰電壓之研究………………………………41
5.1 簡介………………………………………………………………………………41
5.1.1 製程介紹…………………………………………………42
5.1.2 實驗設計…………………………………………………43
5.2 製程設備環境對元件特性之影響……………………… ……44
5.2.1 實驗動機……………………………………………………44
5.2.2 製程環境介紹……………………………………………44
5.2.3 實驗結果與討論…………………………………………45
5.3 晶片與測試鍵之間崩潰電壓差異原因探討………………46
5.3.1 引言………………………………………………………………46
5.3.2 負載效應(Loading Effect) …………47
5.4 改善方式……………………………………………………………………………49
5.4.1 實驗動機………………………………………………………49
5.4.2 實驗結果與討論…………………………………………49
第六章、 結論……………………………………………………………………………………66
參考文獻 ……………………………………………………………………………………………68

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