臺灣博碩士論文加值系統

在通訊系統當中，許多電路需要使用到被動式電感，但隨著半導體技術的發展，射頻積體電路的面積卻受到傳統被動螺旋式電感的限制，藉由主動式電感得以改善品質因數和電感值，並且在晶片製作上，主動式電感需要的面積比被動螺旋式電感還要小。
本篇論文針對分數階微積分的基本介紹，利用電路元件將分數階微積分實體化，並在傳統主動式電感的電路架構中，為了實現分數階的主動式電感，我們將旋相器的電路架構加上BJT元件取代外加電容，根據理論推導及Hspice模擬，我們證實了所提分數階次主動式電感的可行性，也利用電路板做實際量測，並藉由R&S® FSH8手持式頻譜分析儀，量測實際電路的史密斯圖和S參數。

The passive inductors are employed broadly in communication circuits whereas due to the large chip area requirement, the applications of the inductor is resisted in some special circuits such as power amplifiers. On the other hand, active inductors are prevalent due to the tunablity of their quality factor and inductance.
In this thesis, we introduce the fundamentals of fractional-order calculus. To realize the fractional-order active inductors, the conventional gyrator architecture and a bipolar junction transistor (BJT) are employed. The proposed fractional-order active inductor is realized by configuring with a bipolar junction transistor and the architecture of the conventional gyrator. According to the mathematical derivation and Hspice simulation results, the feasibility of the proposed active inductors is validated. The measured S-parameter of the circuit configured with discrete components can also further verify the spectrum of the proposed fractional-order active inductor.

摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章 導論 1
1.1 研究動機 1
1.2 論文組織 2
第二章 分數階的基本微積分 3
2.1 緣起與定義 3
2.2 伽瑪函數 4
2.3 分數階導數的運算 4
2.4 拉普拉斯轉換 5
第三章 分數階元件的實現 6
3.1 分數階電容器 6
3.2 P-N接面的分數階阻抗 7
第四章 被動式電感與主動式電感 9
4.1 被動式電感 9
4.2 主動式電感 10
4.2.1 電感特性 11
4.2.2 旋相器 12
4.2.3 主動式電感 14
4.2.4 模擬結果 15
第五章 分數階主動式電感 19
5.1 分數階電路元件 19
5.2 分數階主動式電感 21
5.3 模擬結果 22
第六章 預測分析與模擬量測 26
6.1 預測分析 26
6.1.1 主動式電感 27
6.1.2 分數階主動式電感 31
6.2 模擬結果 34
6.2.1 主動式電感 34
6.2.2 分數階主動式電感 38
6.3 量測方法 47
第七章 結論與未來研究方向 48
7.1 結論 48
7.2 未來研究方向 48
參考文獻 49

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