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Reference [1] HomeRF Working Group, `` Technical Summary of the SWAP Specification'', March. 1998. [2] S. Wolter, H. Matz, A. Schubert, and R. Laur, `` On the VLSI Implementation of the International Data Encryption Algorithm IDEA'', Circuit and Systems, ISCAS'95 1995., IEEE International Symposium, vol. 1, pp.397-400, 1995. [3] R. Zimmermann, A. Curiger, H. Bonnenberg, `` A 177 Mb/s VLSI Implementation of the International Data Encryption Algorithm'', IEEE Journal Of Solid-State Circuits, VOL. 29, NO. 3, MARCH 1994. [4] A. Curiger, H. Bonnenberg, N. Felber, `` VINCI: VLSI Implementation of the New Secret-Key Block Cipher IDEA'', IEEE Custom Integrated Circuits Conference, 1993. [5] A. Schubert, V. Meyer, and W.Anheier, `` Reusable Cryptographic VLSI Core Based on The Safer K-128 Algorithm with 251.8 Mbit/s Throughput,'' IEEE Signal Processing Systems, 1998. [6] B. Schneier, `` Description of a New Variable-Length Key, 64-Bit Block Cipher(Blowfish)'', Fast Software Encryption, Cambridge Security Workshop Proceedings, Springer-Verlag, pp.191-204, 1994. [7] S.L.C. Salomao, J.M.S. de Alcantara, `` SCOB, a soft-core for the Blowfish cryptographic algorithm'', Integrated Circuit and system Design, 1999. Proceedings. XII Symposium,1999. [8] M.C.J. Lin, Youn-Long Lin, `` A VLSI implementation of the blowfish encryption/decryption algorithm'', Design Automation Conference, 2000. Proceeding of the ASP-DAC 2000. Asia and South Pacific, 2000. [9] A. Schubert, V. Meyer, and W. Anheier, “Reusable Cryptographic VLSI Core Based on The Safer K-28 Algorithm with 251.8 Mbit/s Throught, “ IEEE Signal Processing Systems, 1998. [10] L. Claesen and J. Daemen, “Subterranean: A 600 Mbit/sec Cryptographic VLSI chip”, Computer Design: VLSI in Computers and Processors, ICCD’93 Processing 1993, IEEE International Conference, pp.610-613, 1993. [11] J. Goodman, P. Chandrakasan, “ Low Power scalable encryption for wireless systems”, Wireless Networks 4(1998), pp.55-70, 1998. [12] S. Wolter, H. Matz, A. Schubert, and R. Laur, “ On the VLSI Implementation of the International Data Encryption Algorithm IDEA”, Circuit and Systems, ISCA’95 1995., IEEE International Symposium, vol. 1, pp.397-400, 1995. [13] H. Bonnenberg, A. Guriger, N. Felber, H. Kaeslin, X. Lai, “VLSI Implementation of a New Block Cipher”, Computer Design: VLSI in Computers and Processors, ICCD’91 Proceeding 1991, IEEE International Conference, pp.510-513, 1991. [14] R. Zimmermann, A. Curiger, h. Bonnenberg “ A 177 Mb/s VLSI Implementation of the International Data Encryption Algorithm”, IEEE Journal Of Solid-State Circuits, VOL. 29, NO. 3, MARCH 1994. [15] A. Curiger, H. Bonnenberg, N. Felber, “ VINCI: VLSI Implementation of the New Secret-Key Block Cipher IDEA”, IEEE Custom Integrated Circuits Conference, 1993. [16] D. Runje, M. Kovac, “ Universal Strong Encryption FPGA Core Implementation”, IEEE International Conference, 1998. [17] C.M. Adams, “Symmetric cryptographic system for data encryption, “ U.S. patent 5,511,123, 23 Apr 1996. [18] X. Lai and J. L. Massey, “ A Proposal for a New Block Encryption Standard”, “EUROCRYPT’90’’, Proceedings, pp. 389-404, Springer, 1990. [19] X. Lai, “ On the Design and security of Block Cipher”, Dissertation, ETH Ziirich, No. 9752, 1992. [20] International Standards Organization, “ Information Technology-Modes of operation for a n-block Cipher Algorithm”, ISO/IEC 10116, 1991. [21] I. Verbauwhede, F. Hoornaert, J. Vandewalle, H. De Man, and R. Govaerts, “ Security considerations in the design and implementation of a new DES chip, “ to be published in Proc. Eurocrypt 87 Conf., Springer-Verlag. [22] M. Davio, Y. Desmedt, J. Goubert, F. Hoornaert, and J.-J Quisquater, “Efficient hardware and software implementations of the DES, “ in Advances in Cryptology, Proc. Crypto 84, Aug. 1984. [23] H. Eberle. A high-speed DES implementation for network applications. Technical Report 90, Digitial Equipment Corporation Systems Research Center, September 1992. [24] A.G.Brouscious and J.M.Smith, “ Exploiting Parallelsim in Hardware Implementation of the DES, “ Advances in Cryptography-CRYPTO ’92 Proceedings, Springer-Verlag, 1992, pp.367-376. [25] H. Feistel . Cryptographic and computer Privacy. Scientific American, pages Vol. 30, N. 5, pp.15-23, May 1973. [26] B. Schneier. Applied Cryptography, John Wiley and Sons, New York, NY, 1996. [27] B.E. Briley. Some New Results on Average Worst Case Carry. IEEE Trans. Computers, 22:459-463, May 1973. [28] A.G. Broscius and J.M. Smith, “Exploiting Parallelism in Hard ware Implementation of the DES,” Advances in Cryptologu-CRYPTO ’91 Proceedings, Springer-Verlag,1992, pp.367-376. [29] K. Chong and S. Sartaj, “ Optimal Realizations of Floorplans,” IEEE Transaction on Computer-Aided Design of Integrated Circuit and Systems, VOL. 12. NO. 6. JUNE 1993. [30] T.C. Wang and D.F. Wong, “ Optimal Floorplan Area Optimization, “ IEEE Trans. CAD, vol 11 pp.992-1002 August, 1992.
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