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研究生:鄧君賢
研究生(外文):Jun-Xian Teng
論文名稱:適用在通訊應用知可參數化數位信號處理器資料通路設計
論文名稱(外文):Parameterized and Embedded DSP Datapath for Communication Systems
指導教授:周世傑周世傑引用關係
指導教授(外文):Shyh-Jye Jou
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:84
中文關鍵詞:相關性計算可參數化數位信號處理器資料通路半長度乘法器
外文關鍵詞:datapathDSPsubword multipliercorrelatorparameterizedconfigurable
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摘要
隨著市場的變化越來越快速,晶片設計的時程也變的越來越緊迫,為了能夠在限定時程內完成系統設計,數位訊號處理器可以協助設計人員快速建立系統,然而,全客戶化設計雖耗時較多,卻能夠提供的一定程度的效能提昇。
為了能夠在限定的時間內完成符合目前市場需求以及未來效能提昇的設計,我們提出了可參數化數位訊號處理器設計方法論,並且完成了一系列針對通訊系統設計的特殊功能單元(Special Function Block)。
在資料通路設計(datapath)上,我們針對通訊系統實際應用上對輸入訊號精密度要求的特性,設計了可處理半長度輸入(sub-word input)類型的相乘累加單元,為了能夠利用相同的硬體完成全長度輸入(full-word input)類型的相乘累加,同時兼顧防溢位(overflow)的防護位元(guard bit)運作,我們針對這方面的資料通路設計作了探討。
而在針對通訊系統的應用上,我們提出的可參數化數位訊號處理器可在資料通路及資料讀取上搭配傅立葉運算。另外在相關性運算(correlation)的方面,我們提出了一個為相關性運算所設計的特殊功能單元設計,以及這個特殊功能單元如何與數位訊號處理器共用資料匯流排和加快運算速度。最後,整個可參數化數位處理器的設計流程藉由Visual Basic和C語言所撰寫程式整合在一起。如此一來,藉由可參數化數位訊號處理器搭配上特殊化模組,我們所提出的這種設計方法能夠幫助設計人員建立一個設計環境能夠同時兼顧系統建立的時程以及未來系統效能的提昇。


Abstract
In this thesis, a parameterized DSP datapath design and the parameterized DSP design flow are carried out. The proposed parameterized DSP is composed of DSP itself along with special blocks designed for communication systems. We term this kind processor as parameterized ASIC/DSP core. In the DSP datapath design, a subword MAC path with consideration of guard bit allocation is built for application in two different precision situations. Other than the subword MAC path, a correlator designed for WCDMA system is proposed. The correlator is designed to cooperate with DSP and share the same data bus with DSP.
A parameterized DSP design flow is also proposed in this thesis, we divide issues during a parameterized DSP develop process into three sorts : arguments, control schemes, and structures. These issues are introduced and solved by establish an parameterized DSP generator, which is designed in Visual Basic and C language.


Chapter 1Introduction1
1.1Motivation1
1.2Evolution of Communication DSP Processors3
1.3Wireless Communication-Specific DSP Architecture5
1.4Thesis Organization6
Chapter 2The Design of Data Path7
2.1Introduction7
2.2Overall Structure of NCU_DSP_20028
2.3Status Registers11
2.4The ALU12
2.5The Default MAC Path14
2.6The Dual MAC Path16
2.7The Subword MAC Path17
2.7.1The Subword Multiplier17
2.7.2Sign Extension Consideration20
2.8The Subword Accumulator25
2.8.1Guardbit Allocation Consideration26
2.8.2Structure of Subword MAC Design26
2.9Dual MAC Unit Suitable for Subword29
2.10Summary30
Chapter 3FFT and Correlation31
3.1Introduction of FFT31
3.2FFT Implementation With NCU_DSP32
3.2.1Bit Reversal Addressing Mode32
3.2.2Complex Number Computation33
3.3Introduction of Correlation35
3.4Design of Correlator Special Block Design36
3.4.1Spreading Code and scrambling code36
3.4.2Low Power Correlator Design37
3.4.3Cooperation with NCU_DSP_200240
3.5Summary46
Chapter 4Parameterized Design Flow47
4.1Parameterized Design Flow of NCU_DSP_200247
4.1.1Special Block Identity47
4.1.2Parameters Identity52
4.2DSP Datapath Parameterized Design Flow53
4.2.1Arguments Dependent on Parameters54
4.2.2Control Schemes Dependent on Parameters54
4.2.3Structures Dependent on Parameters55
4.3Summary57
Chapter 5Implementation Results58
5.1Implemented Parameterized Design Flow58
5.2Synthesis Results62
5.2.1First Version of our DSP Core ─ NCU_DSP65
5.3Test Consideration66
5.4Benchmark Simulation67
Chapter 6Conclusion and Future Works69
Reference71


[1]Alan Gatherer, Trudy Stetzler, Mike McMahan, and Edgar Auslander, Texas Instruments, “DSP-Based Architectures for Mobile Communications: Past, Present and Future”[2]I. Verbauwhede and M. Touriguian, "A low power DSP engine for wireless communications," Journal of VLSI Signal Processing Systems, vol. 18, no.2, Feb. 1998[3]TEXAS INSTRUMENTS, TMS320C54x User's Guide[4]http://www.lucent.com/micro/wireless.html[5]J. Nurmi, J. Takala, “A New Generation of Parameterized and Extensible DSP Cores,” IEEE Workshop Procs. on Signal Processing Systems, pp. 320-329, Nov., 1997.[6]Suk Won Kim, MS Thesis : Versatile Low Power Correlator, 1999, University of California, Los Angeles.[7]B.W.Kim, J.H.Ynag, C.S.Hwang, Y.S.Kwon, K.M.Lee, I.H.Kim, Y.H.Lee, C.M.Kyung,“MDSP-II: a 16-bit DSP with Mobil Communication Accelerator”. IEEE J.Solid-States Circuits, 34(3):397-403,Mar 1999.[8]M.Kuulusa, J.Nurmi, J.Jakala, P.Ojala, H.Herranen, “A Flexible DSP Core for Embedded Systems,” IEEE Design & Test of Computers, Vol14, No.4, pp.60-68, Oct.-Dec., 1997,.[9]“A New Generation of Parameterized and Extensible DSP Cores,” IEEE Workshop Procs. on Signal Processing Systems, pp. 320-329, Nov., 1997. [10]Verbauwhede and M. Touriguian, “A low power DSP engine for wireless communications” Journal of VLSI Signal Processing Systems, vol.18, no.2, Feb.1998[11]H.P.Lee, MS Thesis : Embedded DSP Core for Communication System. Dep. Elec. Eng., National Central University, Taiwan, June, 2001.[12]Y.T.Chen, MS Thesis : Embedded DSP Datapath for Communication System. Dep. Elec. Eng., National Central University, Taiwan, June, 2001.[13]J. Warden, “Sub-Word Parallelism in Digital Signal Processing”, IEEE Signal Processing Magazine, March, pp.27-35, 2000.[14]Y.H.Huang, “Design and Implementation of A Communication Digital Signal Processor for OFDM-Based Software Radio”, National Taiwan University, Taiwan, May, 2001.[15]R.E.Ziemer, W.H.Tranter, “Principles of Communications, Systems, Modulation, and Noise, Fourth Edition” JOHN WIELY&SONS, INC.[16]“Spreading Spectrum introduction and applications” ir.J.Meel, Sirius Communications, Rotselaar, Belgium.[17]3G TS 25.211, “Physical Channels and Mapping of Transport Channels onto Physical Channels(FDD),” 3GPP Technical Specification, Version 5.0.0, Mar, 2002[18]3G TS 25.213 “Technical Specification Group Radio Access Network.” 3rd Generation Partnership Project, 3GPP Technical Specification, Version 5.0.0, Mar, 2002[19]3G TS 25.214 “Technical Specification Group Radio Access Network; Physical layer procedures (FDD).” 3rd Generation Partnership Project, 3GPP Technical Specification, Version 5.0.0, Mar, 2002 [20]Giridhar D. Mandyam and Jersey Lai, Academic Press, “Third Generation CDMA Systems for Enhanced Data Services”, chapter6, WCDMA Overview, 2002[21]A.Chandrakasan and R.Brodersen, “Minimizing Power Consumption in Digital CMOS Circuits”, Proc. of the IEEE, Vol.83, No.4, Apr.1995, pp.498-523[22]M.Ercegovacc and T.Lang, “Low-Power Accumulator(Correlator)”, IEEE Symp. on Low Power Electronics, Digest of Technical Papers, Oct. 1995, pp.30-31[23]Suk Won Kim, “Versatile Low Power Correlator” 1999, University of California, Los Angeles.[24]Ming Hsuan Tan. “Parameterized and Embedded DSP Core for Communication applications”[25]M.C.Liu, C.L.Chen, D.Y.Shin, C.H.Lin, S.J.Jou, “Low-power multiplierless FIR filter synthesizer based on CSD code”, IEEE International Symp. on Circuits and Systems (ISCAS), pp666-669, 2001[26]DesignWare Cell Library Online Document[27]ALTERA, Application Note 129, September 2000, ver1.0 “Implementing a W-CDMA System with Altera Devices & IP Functions”

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