臺灣博碩士論文加值系統

在2001年12月，國際研究組織ITU-T VCEG與ISO/IEC MPEG共同組成聯合視訊小組的JVT，研訂了新的視訊編碼標準，此一標準在ITU-T組織稱為H.264，而ISO組織則納入MPEG-4 Part-10，並命名為AVC。H.264/AVC在編碼效率上有顯著的改善，而移動估測是視訊編碼的核心，其中可變區塊大小移動估測（Variable Block Size Motion Estimation）是一項新的影像編碼技術，主要改善了因為影像編碼所造成的失真，提供較準確的預測，減少影像編碼的資料量，增加網路頻寬的利用率。
在此篇論文，我們提出可變區塊大小移動估測之平行超大型積體電路架構應用於全域搜尋區塊比對演算法（Full Search Block Matching Algorithm）。移動估測架構以管線化設計平衡各階段執行時間以提高效能，再規劃成平行處理模式去改善資料產出量，以利後續運算盡早進行，因應管線化機制，在處理單元方面採用階層式架構去計算七種區塊（4×4、8×4、4×8、8×8、16×8、8×16以及16×16），使電路簡單以及降低計算複雜度。使用硬體描述語言撰寫並驗證功能性，再透過TSMC 0.18μm CMOS製程，將電路合成以及實體佈局，並完整呈現整體之晶片設計，以驗證本論文所提出的平行架構之可行性。實驗結果顯示，本論文所提出的移動估測之平行架構，具有提高效能以及降低運算複雜度的特性。

The H.264/AVC video coding standard was recently developed by the Joint Video Team (JVT) consisting of experts from international study groups, Video Coding Experts Group (VCEG) and Moving Picture Experts Group (MPEG), which significantly improves video coding. Motion estimation is one of the core designs of the H.264/AVC video coding. Variable block size motion estimation (VBSME) is a new video coding technique which improves video distortion, provides more accurate predictions, reduces video coding data, and increases the utilization of network bandwidth.
This thesis proposes parallel VLSI architectures for VBSME which apply to the full search block matching algorithm (FSBMA). Our proposed architecture use pipelined design to balance the execution time of each stage in order to increase the performance. Furthermore, our design employs parallel architectures to improve the throughput, and facilitate lower computation time.
With the pipelined design, the processing elements use hierarchical structures to calculate seven kinds of blocks (4×4, 8×4, 4×8, 8×8, 16×8, 8×16, and 16×16), which have relatively simple circuits and relatively low computation complexity. We use cell-based design with TSMC 0.18 μm CMOS technology to implement our hardware. Our proposed architecture is realized with physical design flow to show its feasibility. Experimental results show that our proposed parallel architectures can increase the performance and reduce the computational complexity compared to other designs.

摘要 I
Abstract II
目錄 III
圖目錄 V
表目錄 IX
第一章 導論 1
1.1 動機 1
1.2 論文組織 2
第二章 研究背景 3
2.1 H.264/AVC標準簡介 3
2.2 可變區塊大小 9
2.3 移動估測 10
2.4 區塊比對演算法 10
2.4.1 全域搜尋區塊比對演算法 12
2.4.2 三步搜尋演算法 13
2.4.3 鑽石搜尋演算法 15
2.5 可變區塊大小移動估測架構 17
2.5.1 Work of Yang et al. 17
2.5.2 Work of Yap and McCanny 20
2.5.3 Work of Jinwook Kim and Taegeun Park 23
第三章 移動估測VLSI架構設計 25
3.1 移動估測之平行架構 25
3.2 處理單元 27
3.2.1 圖塊分割 31
3.2.2 掃描序列 31
3.2.3 資料流程 33
3.2.4 41 SAD值 36
3.3 最小SAD值運算 36
3.4 移動估測記憶體架構 39
4.1 實驗環境 42
4.2 RTL模擬結果 45
4.2.1 處理單元時序模擬 45
4.2.2 移動估測記憶體時序模擬 48
4.2.3 移動估測SAD值運算時序模擬 49
4.3 電路合成結果 51
4.4 合成實驗數據分析 54
4.5 實體佈局結果 60
第五章 結論 64
參考文獻 65

[1]“Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264 | ISO/IEC 14496-10 AVC),” Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVT-G050, 2003.
[2]C. Y. Chen, S. Y. Chien, Y. W. Huang, T. C. Chen, T. C. Wang, and L. G. Chen, “Analysis and Architecture Design of Variable Block Size Motion Estimation for H.264/AVC,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, no. 3, pp. 578-593, Mar. 2006.
[3]C. P. Fan, “Fast 2-Dimensional 4x4 Forward Integer Transform Implementation for H.264/AVC,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 3, pp. 174-177, Mar. 2006.
[4] C. L. Hsu, M. H. Ho, and M. K. Liu, “High-Efficient Mode-Decision Design for Motion Estimation in H.264,” IEEE International Conference on Consumer Electronics, Jan. 2007.
[5]Y. W. Huang, T. C. Wang, B. Y. Hsieh, and L. G. Chen, “Hardware Architecture Design for Variable Block Size Motion Estimation in MPEG-4 AVC/JVT/ITU-T H.264,” Proceedings of the International Symposium on Circuits and Systems, vol. 2, pp. 796-799, 2003.
[6]X. Jing and L. P. Chau, “An Efficient Three-Step Search Algorithm for Block Motion Estimation.” IEEE Transactions on Multimedia, vol. 6, pp. 435-438, June 2004.
[7]M. Kim, I. Hwang, and S. I. Chae, “A Fast VLSI Architecture for Full-search Variable Block Size Motion Estimation in MPEG-4 AVC/H.264,” Proceedings of the Asia and South Pacific on Design Automation Conference, vol. 1, pp. 631-634, Jan. 2005.
[8]J. Kim and T. Park, “A Novel VLSI Architecture for Full-SearchVariable Block-Size Motion Estimation,” IEEE Transactions on Consumer Electronics, vol. 55, pp. 728-733, May 2009.
[9]S. K. Kwon, A. Tamhankar, and K. R. Rao, “Overview of H.264/MPEG-4 part 10,” Journal of Visual Communication and Image Representation, vol. 17, pp. 186-216, April 2006.

[10]R. Li, B. Zeng, and M. L. Liou, “A New Three-Step Search Algorithm for Block Motion Estimation,” IEEE Transactions on Circuits Systems and Video Technolong, vol. 4, pp. 438-442, Aug. 1994.
[11]Z. Liu, Y. Huang, Y. Song, S. Goto, T. Ikenaga, “Hardware -Efficient Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC,” Proceedings of the 17th ACM Great Lakes symposium on VLSI, pp. 160-163, Mar. 2007.
[12]K. M. Yang, M. T. Sun, and L. Wu, “A Family of VLSI Designs for the Motion Compensation Block-Matching Algorithm,” IEEE Transactions on Circuits and Systems, vol. 36, no. 10, pp. 1317-1325, Oct. 1989.
[13]S. Y. Yap and J. V. McCanny, “A VLSI Architecture for Variable Block Size Video Motion Estimation,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 51, pp. 384-389, July 2004.
[14]T. C. Wang, Y. W. Huang, H. C. Fang, and L. G. Chen, “Parallel 4x4 2D Transform and Inverse Transform Architecture for MPEG-4 AVC/H.264,” Proceedings of the International Symposium on Circuits Systems, vol. 2, pp. 800-803, May 2003.
[15]T. Wiegand, G. J. Sullivan, G. Bjontegaard, and A. Luthra, “Overview of the H.264/AVC Video Coding Standard,” IEEE Transactions on Circuits and System for Video Technology, vol. 13, no. 7, pp. 560-576, July 2003.
[16]S. Zhu and K. K. Ma, “A New Diamond Search Algorithm for Fast Block-Matching Motion Estimation,” IEEE Transactions on Image Processing, vol. 9, no. 2, pp. 287-290, Feb. 2000.
[17]郭其昌, “H.264先進視訊編解碼標準,” 數位視訊多媒體月刊, 民94。
[18]趙維民, “視訊訊號處理之移動估計及其架構,” IC設計月刊, 2001.11月號。