臺灣博碩士論文加值系統

目前主流的數位VLSI設計和邏輯電路合成軟體，皆以互補式金氧半導體(CMOS)邏輯為主，但是在許多應用上，以開關電晶體邏輯（Pass-Transistor Logic, PTL）為主的邏輯電路設計，在面積、速度及功率等方面，均有優異的表現。雖然開關電晶體已經可以達到良好的效能，但目前電路設計自動化軟體工具，在合成電路時考量速度/功率/面積之最佳化時，都是以CMOS電路為主，因此現有的邏輯合成器並無法有效產生PTL電路。本篇論文將提出兩種新的PTL電路合成器設計，其中一種是採用純粹PTL邏輯元件來設計元件電路，另一種則是加入混合PTL/CMOS電路元件來達到在面積、速度及功率等方面更好的結果。開關電晶體電路只須要少數幾種基本電路元件設計和佈局，就能合成所有的電路，因此很適合在製程技術日新月異的奈米時代用來合成單晶片系統（System-on-a-Chip, SoC）。我們所提的PTL邏輯合成器使用Synopsys 設計編譯器 (Design Compiler, DC)，利用標準元件庫的邏輯元件來進行邏輯轉換以及製程對應 (technology mapping)，因此更能有效的嵌入在特殊積體電路標準元件設計流程 (ASIC cell-based design flow)。此篇論文也將探討PTL電路在一些基本的硬體模組設計，以及在算術運算單元及三維繪圖處理器上之應用。

The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, in the past two decades, various new logic circuit design styles based on pass-transistor logic (PTL) have been proposed. Compared with CMOS circuits, these PTL-based circuits are claimed to have better results in area, speed, and power in some particular applications, such as adder and multiplier designs. Since most current automatic logic synthesis tools (such as Synopsys Design Compiler) are based on conventional CMOS standard cell library, the corresponding logic minimization for CMOS logic cannot be directly employed to generate efficient PTL circuits. In this dissertation, we develop two novel PTL synthesizers that can efficiently generate PTL-based circuits. One is based on pure PTL cells; the other mixes CMOS and PTL cells in the standard cell library to achieve better performance in area, speed, and power. Since PTL-based circuits are constructed by only a few basic PTL cells, the layouts in PTL cells can be easily updated to design large SoC systems as the process technology migrates rapidly in current Nano technology era. The proposed PTL logic synthesis flows employ the popular Synopsys Design Compiler (DC) to perform logic translation and minimization based on the standard cell library composed of PTL and CMOS cells, thus, the PTL design flow can be easily embedded in the standard cell-based ASIC design flow. In this dissertation, we also discuss PTL-based designs of some fundamental hardware components. Furthermore, the proposed PTL cell library is used to synthesize large processor systems in applications of computer arithmetic and 3D graphics.

Acknowledgement i
摘要 ii
Abstract iii
Table of Contents iv
List of Figures vii
List of Tables xi
Chapter 1 Introduction 1
Chapter 2 Survey of Related Works 6
2.1 PTL Circuit Design 6
2.1.1 Previous PTL Circuits 6
2.1.2 PTL vs. CMOS 11
2.2 Pure PTL Synthesis 12
2.3 Hybrid PTL/CMOS Synthesis 14
2.4 Benchmark Circuits 15
Chapter 3 PTL Synthesis with Buffer Elimination 16
3.1 Proposed PTL Synthesis Flow 16
3.1.1 Basic PTL Cells 16
3.1.2 Circuit Design of PINV 17
3.1.3 Overall PTL Synthesis Flow 19
3.2 Technology Mapping Based on PTL Cells 19
3.2.1 One-Level PTL Cells 19
3.2.2 Multi -Level PTL Cells 22
3.3 PTL Logic Simplification 26
3.3.1 Logic Minimization 26
3.3.2 Buffer Elimination 28
3.4 Layout Compaction 31
3.4.1 Separation of Rows for MUX and PINV 33
3.4.2 Merging of Basic PTL Cells 33
3.5 Experimental Results and Comparison 36
3.6 Summary 42
Chapter 4 Hybrid PTL/CMOS Synthesis with Multi-Level PTL Logic 44
4.1 Proposed Hybrid PTL/CMOS Logic Synthesis Flow 44
4.2 Basic PTL Physical Cells 46
4.3 PTL Logic Cells 46
4.3.1 One-Level Logic Cells 46
4.3.2 Multi-Level Logic Cells 48
4.3.3 Some Improvements for PTL Logic Cells 50
4.4 Characterization of PTL Logic Cells 51
4.5 Experimental Results and Comparison 55
4.6 Comparison of Two PTL Synthesis Methods 59
4.7 Summary 63
Chapter 5 PTL Designs for Some Fundamental Circuits 64
5.1 Multiple-Input XOR/XNOR Circuit Design in Cryptography 64
5.1.1 Design of XOR with Multiple Inputs 65
5.1.2 Experimental Results and Comparison 68
5.1.3 Application in AES Design 69
5.2 Design of Full Adder and (4,2) Compressor 71
5.2.1 Full Adder Design 71
5.2.2 Design of (3,2) Counter and (4,2)Compressor Circuits 73
5.3 D Flip-Flop for PTL 79
5.4 Decoder Design 81
5.4.1 Novel PTL Decoder Design 82
5.5 Summary 89
Chapter 6 Applications to the Design of Arithmetic Units and 3D Graphics Processors 90
6.1 Three-Stage ROM/Multiplier-Based CORDIC 90
6.1.1 Original CORDIC Algorithm 90
6.1.2 Multiplier/ROM-Based Implementations 91
6.1.3 Experimental Results and Comparison 98
6.2 Reciprocal Function Evaluation with Hybrid Piecewise Polynomial Approximation and Newton-Raphson Method 100
6.2.1 Hybrid Piecewise Polynomial Approximation and Newton-Raphson Method 100
6.2.2 Unified Architecture 102
6.2.3 Sub-Word-Sharing Architecture 104
6.2.4 Experimental Results and Comparison 107
6.3 3D Graphics Processors 108
6.3.1 Overview of 3D Graphics Pipeline 108
6.3.2 Hardware of Vertex Shader 110
6.3.3 Experimental Results and Comparison 113
6.4 Summary 115
Chapter 7 Conclusions and Future Works 116
7.1 Conclusions 116
7.2 Future Works 116
Bibliography 120

[1] N.-H.-E. Weste and D. Harris, CMOS VLSI Design, A Circuits and Systems Perspective, Third Edition, Addison-Wesley Publisher, 2005, ISBN: 0-321-26977-2.
[2] C.-Y. Wu, J.-S. Wang and M.-K. Tsai, “The analysis and design if CMOS multidrain logic and stacked multidrain logic,” IEEE Journal of Solid-State Circuits (JSSC), Vol.SC-22, No.1, pp.47-56, Feb. 1987.
[3] I.-S. Abu-Khater, A. Bellaouar and M.-I. Elmasry, ”Circuit Techniques for CMOS Low-Power High-Performance Multipliers,” IEEE Journal of Solid-State Circuits (JSSC), Vol.31, No.10, pp.1535-1546, Oct. 1996.
[4] L. Heller, W. Griffin, J. Davis and N. Thoma, “Cascode Voltage Switch Logic：A Differential CMOS Logic Family,” Proc. IEEE Intl. Conf. on Solid-State Circuit, pp.16-17, Feb. 1984.
[5] R.-H. Krambeck, C.-M. Lee and H.-S. Law, ”High-Speed Compact Circuits with CMOS,” IEEE Journal of Solid-State Circuits (JSSC), Vol. SC-17, pp.614-619, June 1982.
[6] A. Jaekel, S. Bandyopadhyay and G.-A. Jullien, ”Design of Dynamic Pass-Transistor Logic Circuits Using 123 Decision Diagrams,” IEEE Trans. on Circuits and Systems I, Vol. 45, No. 11, pp. 1172 –1181, Nov. 1998.
[7] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu and J. Yamada, “1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS,” IEEE Journal of Solid-State Circuits(JSSC), Vol.30, No.8, pp.847-854, Aug. 1995.
[8] J.-H. Pasternak and C.-A.-T. Salama, ”Differential Pass-Transistor Logic,” IEEE Circuits and Devices Magazine, Vol. 9, No. 4, pp.23-28, July 1993.
[9] A. Parameswar, H. Hara and T. Sakurai, “A Swing Restored Pass-Transistor Logic-Based Multiply and Accumulate Circuit for Multimedia Applications,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 31, No. 6, pp. 804-809, June 1996.
[10] F.-S. Lai and W. Hwang, “Design and Implementation of Differential Cascode Voltage Switch with Pass-Gate (DCVSPG) Logic for High-Performance Digital Systems,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 32, No. 4, pp. 563-573, Apr. 1997.
[11] T.-S. Cheung and K. Asada, “Regenerative pass transistor logic: A circuit technique for high speed digital design, “IEICE Trans. Electron., E79-C(9):1274–1283, 1996.
[12] K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi and A. Shimizu, “A 3.8-ns CMOS 16x16-b Multiplier Using Complementary Pass-Transistor Logic,” IEEE Journal of Solid-state Circuits (JSSC), Vol. 25, No. 2, pp. 388-395, Apr. 1990.
[13] M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki and Y. Nakagome, ”A 1.5 ns 32 b CMOS ALU in Double Pass-Transistor Logic,” IEEE Journal of Solid-State Circuits (JSSC), Vol.28, No.11, pp.1145-1150, Nov. 1993.
[14] P. Buch, A. Narayan, A.-R. Newton and A.-L. Sangiovanni-Vincentelli, “Logic synthesis for large pass transistor circuits,” Proc. IEEE Intl. Conf. on CAD (ICCAD), pp. 663–670, 1997.
[15] M. Yano, Y. Sasaki, K. Rikino and K. Seki, “Top-down Pass-Transistor Logic Design,” IEEE Journal of Solid-State Circuits (JSSC), Vol.31, No. 6, pp.792-803, June 1996.
[16] R.-S. Shelar and S.-S. Sapatnekar, “BDD Decomposition for Delay Oriented Pass Transistor Logic Synthesis”, IEEE Trans. VLSI Systems, Vol. 13, No. 8, pp. 957-970, Aug. 2005.
[17] S. Goel, A. Kumar and M.-A. Bayoumi, ”Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style”, IEEE Trans. VLSI Systems, Vol. 14, No. 12, pp. 1309-1321, Dec. 2006.
[18] S. Agarwal, V.-K. Pavankumar and R. Yokesh, “Energy-Efficient, High Performance Circuits for Arithmetic Units”, Proc. IEEE Intl. Conf. on VLSI Design, pp. 371-376, 2008.
[19] J.-F. Lin, Y.-T. Hwang, M.-H. Sheu and C.-C. Ho, “A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design”, IEEE Trans. Circuits and Systems I, Vol. 54, No. 5, pp.1050-1059, May 2007.
[20] R. Zimmermann and W. Fichtner, “Low Power Logic Styles: CMOS versus Pass-transistor Logic,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 32, No. 7, pp. 1079-1089, July 1997.
[21] C. Scholl and B. Becker, “On the generation of multiplexer circuits for pass transistor logic,” Proc. Design, Automation and Test in Europe Conference and Exhibition, pp. 372 – 378, 2000.
[22] G.-R. Cho and T. Chen, “Synthesis of Single/Dual-Rail Mixed PTL/Static Logic for Low-Power Applications,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 2, pp. 229-242, Feb. 2004
[23] S.-B. Akers, “Binary Decision Diagram,” IEEE Trans. Computers, vol. C-27, No. 6, pp. 509-516, June 1978.
[24] M. Song, G. Kang, S. kim and B. Kang, “Design methodology for high speed and low power digital circuits with energy economized pass-transistor logic (EEPL),” Proc. 22nd European Conf. on Solid-State Circuits, pp.120-123, 1996.
[25] W. Paik, H. Ki and S. Kim, “Push-pull pass-transistor logic family for low voltage and low power,” Proc. 22nd European Conf. on Solid-State Circuits, pp.116-119, 1996
[26] T.-H. Liu, A. Aziz and J.-L. Burns, “Performance driven synthesis for pass-transistor logic,” Proc. Intl. Workshop on Logic Synth., pp. 255–259, 1998.
[27] R. Chaudhry, T.-H. Liu, A. Aziz and J.-L. Burns, “Area oriented synthesis for pass-transistor logic,” Proc. Intl. Conf. on Comp. Design, pp. 160–167, 1998.
[28] P. Lindren, M. Kerttu, M. Thornton and R. Drechsler, “Low Power Optimization Technique for BDD Mapped Circuits,” Proc. Asia and South Pacific Conf. on Design Automation, pp.615-621, Feb. 2001.
[29] M. Avci and T. Yildirim, “ General design method for complement pass transistor logic circuits,” Electronics Letters, Vol. 39, No. 1, pp. 46-48, Jan. 2003.
[30] C. Yang and M. Ciesielski , “BDS: a BDD-based logic optimization system,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.21, No.7, pp. 866-876, July 2002.
[31] K. Yip and D. Al-Khalili, “Multilevel logic synthesis using hybrid pass logic and CMOS topologies,” Proc. IEE Conf. on Circuits, Devices and Systems, Vol. 150, no. 5, pp. 445-452, Oct. 2003.
[32] Y. Jiang, S.-S. Sapatnekar and C. Bamji, ”Technology Mapping for High-Performance Static CMOS and Pass Transistor Logic Designs,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol.9, No.5, pp.577 –589, Oct. 2001.
[33] R.-S. Shelar and S.-S. Sapatnekar, “Recursive bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic,” Proc. IEEE Intl. Conf. on CAD (ICCAD), pp. 449 – 452, Nov. 2001.
[34] Y. Sasaki, K. Yano, S. Yamashita, H. Chikata, K. Rikino, K. Uchiyama and K. Seki, “Multi-level pass-transistor logic for low-power ULSIs,” Proc. Intl. Symp. on Low power Electronics, pp. 14–15, Oct. 1995.
[35] S. Yanashita, K. Yano, Y. Sasaki, Y. Akita, H. Chikata, K. Rikino and K. Seki, “Pass-transistor/CMOS collaborated logic: The best of both worlds,” Proc. Symp. on VLSI Circuits, Digest Technical Papers, pp. 31–32, 1997.
[36] C. Yang and M. Ciesielski, “Synthesis for mixed CMOS/PTL logic,” Proc. Europe Conf. and Exhibition on Design, Automation and Test, pp.750, 2000.
[37] J.-D. Meindl, “Gigascale integration: Is the sky the limit?,” IEEE Circuits and Devices Magazine, Vol. 12, pp. 19–32, Nov. 1996.
[38] J.-M. Rabaey, Digital Integrated Circuits. Englewood Cliffs, NJ: Prentice-Hall, 1996.
[39] F. Brglez and H. Fujiwara, “A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran,” Proc. IEEE Intl. Symp. on Circuits and Systems, pp. 695-698, June 1985.
[40] F. Brglez, D. Bryan and K. Kozminski, “Combinatorial Profiles of Sequential Benchmark Circuits,” Proc. IEEE Intl. Symp. on Circuits and Systems, pp. 1929-1934, 1989.
[41] S. Yang, “Logic synthesis and optimization benchmarks user guide version 3.0,” Tech. Rep., Microelectronics Center of North Carolina, P. O. Box 12889, Research Triangle Park, NC 27709, 1991.
[42] E.-J. Marinissen, V. Iyengar and K. Chakrabarty, “A Set of Benchmarks for Modular Testing of SOCs,” Proc. of IEEE Intl. Conf. on Test (ITC''02), pp. 519-528, Oct. 2002.
[43] A. Reis, R. Reis, D. Auvergne and M. Robert, “The library free technology mapping problem,” Proc. IEEE/ACM Intl. Workshop on Logic Synthesis (IWLS), Lake Tahoe, CA, pp. 7.1.1-7.1.5, June 1997.
[44] F. Ferrand, A. Macii, E. Macii, M. Poncino, R. Scarsi and F. Somenzi, “Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits,” Proc. Intl. Conf. on CAD (ICCAD), pp. 235-241, 1998.
[45] “Advanced Encryption Standard (AES),” Federal Information Processing Standards Publication 197, available at http://www.nist.gov/CryptoToolkit, Nov. 26, 2001.
[46] J.-M. Wang, S.-C. Fang and W.-S. Feng, “New Efficient Designs for XOR and XNOR functions on the Transistor Level,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 29, No. 7, pp. 780-786, 1994.
[47] H.-T. Bui, Y. Wang and Y. Jiang, “Design and Analysis of Low-power 10-transistor Full Adders Using XOR/XNOR Gates,” IEEE Trans. On Circuits and Systems II, Vol.49, No. 1, pp. 25-30, Jan. 2002.
[48] S. Goel, M.-A. Elgamel and M.-A. Bayoumi, “Novel Design Methodology for High-performance XOR-XNOR Circuit Design,” Proc. of the 16th Symp. on Integrated Circuits and Systems Design, pp.71-76, Sept. 2003.
[49] Y.-C. Cheng, “ Table-Based Design of Arithmetic Function Units for Angle Rotation and Rectangular-to-Polar-Coordinate Conversion,” MS thesis, Dept. of Computer Science and Engineering., National Sun Yat-sen University, 2009.
[50] R. Shalem, E. John and L. K. John, “A novel low-power energy recovery full adder cell,” Proc. Symp. in VLSI, pp. 380–383, Feb., 1999.
[51] G. Gerosa, S. Gary, C. Dietz, P. Dac, K. Hoover, J. Alvarez, H. Sanchez, P. Ippolito, N. Tai, S. Litch, J. Eno, J. Golab, N. Vanderschaaf and J. Kahle, “A 2.2W, 80MHz superscalar RISC microprocessor,” IEEE J. Solid-State Circuits (JSSC), Vol. 29, No. 12 pp. 1440–1454, Dec. 1994.
[52] U. Ko and P.-T. Balsara, “High-Performance Energy-Efficient D-Flip-Flop Circuits,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 1, pp. 94 –98, Feb. 2000.
[53] I.-C. Hwang and S.-M. Kang, "Differential pass-transistor clocked flipflop", Electronics Letters, Vol. 37, No. 12, pp.732 – 734, Jun 2001.
[54] V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel and F. Baez, “Reducing power in high-performance microprocessors,” in Proc. Design Automation Conf. (DAC), pp. 732–737, 1998.
[55] R. Heald, K. Shin, V. Reddy, K. I-Feng, M. Khan, W.-L. Lynch, G. Lauterbach and J. Petolino, “ 64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 33, No. 11, pp.1682 – 1689, Nov. 1998.
[56] R. Lyon and R. Schediwy, “CMOS static memory with a new four-transistor memory cell,” Proc. Advanced Research in VLSI, pp.111-132, Mar. 1987.
[57] M. Yoshimoto, K. Anami, H. Shinohara, T. Yoshihara, H. Takagi, S. Nagao, S. Kayano and T. Nakano, “A 64Kb CMOS RAM with divided word line structure,” Proc. IEEE Intl. Conf. on Solid State Circuits, pp. 58-59, 1983.
[58] O. Minato, T. Masuhara, T. Sasaki, H. Nakamura, Y. Sakai, T. Yasui and K. Uchibori, “2K x 8 bit Hi-CMOS static RAM’s”, IEEE Journal of Solid State Circuits (JSSC), vol. SC-15, no. 4, pp. 656-660, Aug. 1980.
[59] Y. Kohno, T. Wada, K. Anami, Y. Kawai, K. Yuzuriha, T. Matsukawa and S. Kayano, “A 14-ns 1-Mbit CMOS SRAM with variable bit organization,” IEEE Journal of Solid State Circuits (JSSC), Vol. 29, No. 9, pp. 1060-1065, Oct. 1988.
[60] T.-I. Chappell, B.-A. Chappell, S.-E. Schuster, J.-W. Allan, S.-P. Klepner, R.-V. Joshi and R.-L. Franch, “A 2-ns Cycle, 3.8-ns Access 512-Kb CMOS ECL SRAM with a Fully Pipelined Architecture,” IEEE Journal of Solid State Circuits (JSSC), Vol. 26, No.11, pp. 1577-1585, Nov. 1991.
[61] G. Braceras, D. Evans, J. Sousa and J. Conner, “A 350MHz 3.3V 4Mb SRAM fabricated in a 0.3μm CMOS process,” Proc. IEEE Intl. Conf. on Solid State Circuits, pp. 404-405. 1997.
[62] H. Nambu, K. Kanetani, K. Yamasaki, K. Higeta, M. Usami, T. Kusunoki, K. Yamaguchi and N. Homma, “A 1.8 ns access, 550 MHz 4.5 Mb CMOS SRAM,” Proc. IEEE Intl. Conf. on Solid State Circuits, pp.360–361, 1998.
[63] B. Amrutur and M. Horowitz, “A replica technique for word line and sense control in low-power SRAMs,” IEEE Journal of Solid State Circuits, Vol. 33, No. 8, pp.1208-1219, Aug. 1998.
[64] B.-S. Amrutut and M.-A. Horowitz, “Fast low-power decoders for RAMs,” IEEE Journal of Solid-State Circuits (JSSC), Vol.36, No. 10, pp. 1506 – 1515, Oct. 2001.
[65] H.-C. Park, S.-K. Yang, M.-C. Jung, T.-G. Kang, S.-C. Kim, K.-M. Sohn, D.-G. Bae, S.-S. Kim, K.-H. Kim, B.-S. Sohn, H.-S. Kim, H.-G. Byun, Y.-S. Shin and H.-K. Lim, “A 833Mb/s 2.5V 4Mb double data rate SRAM,” Proc. IEEE Intl. Conf. on Solid State Circuits, pp.356-357. 1998.
[66] R. Heald and J. Holst, “A 6-ns cycle 256kb cache memory and memory management unit,” IEEE Journal of Solid State Circuits (JSSC), Vol. 28, pp. 1078-1083, Nov. 1993.
[67] K. Nakamura, K. Takeda, H. Toyoshima, K. Noda, H. Ohkubo, T. Uchida, T. Shimizu, T. Itani, K. Tokashiki and K. Kishimoto, “A 500MHz 4Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O,” IEEE Journal of Solid State Circuits (JSSC), Vol. 32, No. 11, pp. 1758-1765, Nov. 1997.
[68] A. Munshi, “Opengl ES Common/Common-Lite Profile Specification”, Ver. 1.1, Nov. 2004.
[69] A. Munshi, “Opengl ES Common/Common-Lite Profile Specification”, Ver. 2.0, Nov. 2004.
[70] K.-M. Huang, “ Design, Implementation, And Verification of A Programmable Floating- And Fixed- Point Vertex Shader,” MS Thesis, Dept. of Computer Science and Engineering, National Sun Yat-sen University, 2009.
[71] J-A Pineiro, S.-F. Oberman, J.-M. Muller and J.-D. Bruguera, “High-Speed Function Approximation Using a Minimax Quadratic Interpolator,” IEEE Trans. on Computers, Vol. 54, No. 3, pp. 304-318, Mar. 2005.
[72] E.-G. Walters-III and M.-J. Schulte, “Efficient Function Approximation Using Truncated Multipliers and Squarers,” Proc. IEEE 17th Symp. On Computer Arithmetic, pp. 232-239, 2005.
[73] J.-E. Voder, “The CORDIC Trigonometric Computer Technique,” IRE Trans.. Electron. Computers, vol. EC-8, no. 3, pp. 330-334, Sept. 1959.
[74] P.-K. Meher, J. Valls, T.-B. Juang, K. Sridharan and P.-K. Meher, "50 Years of CORDIC: Algorithms, Architectures and Applications," IEEE Transactions on Circuits and Systems I, Vol. 56, No. 9, pp. 1893-1907, Sep. 2009.
[75] “Berkeley predictive technology model,” available at http://www.eas.asu.edu/~ptm/.