臺灣博碩士論文加值系統

本論文是以TSMC 0.18 μm CMOS 製程，研製應用於超寬頻(UWB)系統之低雜訊放大器。論文中使用兩種電路架構，一個為採用電流再利用架構來達到低功率消耗的目的，另一個為兩階的cascode架構加上inter-stage network達到高增益的效果。

第一部份的設計，量測結果在直流功率消耗 9.2mW時可以得到最大增益為 13.2 dB，3-dB 頻寬為3.1 – 10.6 GHz，最低雜訊指數為 3.33 dB，在頻帶內輸入反射損耗均小於 -10.3 dB，三階截斷點大於 -3.3 dBm，其晶片面積為 0.91 mm2。

第二部份的寬頻低雜訊放大器，模擬結果在直流功率消耗 14.2 mW 時可以得到最大增益為 21.2 dB，3-dB 頻寬為 3.1 – 10.6 GHz，最低雜訊指數為 3.6 dB，在頻帶內輸入反射損耗均小於 -12.4 dB，三階截斷點大於 -17dBm，其晶片面積為 1.05 mm2。

In this thesis, we design two broadband low noise amplifiers (LNAs) for ultra-wideband (UWB) communication systems, which are implemented in TSMC 0.18 μm CMOS technology. The design of the amplifiers concentrates on low power-consumption and low costs as well. The first design utilizes a current topology to save the power and the second design is used two stage cascade topology with a inter-stage network to achieve the high gain performance.

In the first section, the measurement of the first LNA shows that the maximum gain is 13.2 dB, 3-dB bandwidth is from 3.1 GHz to 10.6 GHz, the minimum noise figure is 3.33 dB, S11 is less than -10.3dB, IIP3 is better than -3.3 dBm, and the total power consumption is 9.2 mW. The chip size is 0.91 mm2.

In the second section, the simulated maximum gain is 13.2 dB, 3-dB bandwidth is from 3.1 GHz to 10.6 GHz, the minimum noise figure is 3.6 dB, S11 is less than -12.4 dB, IIP3 is better than -17 dBm, and the total power consumption is 14.2 mW. The chip size is 1.05 mm2.

中文摘要 .................................................................................................... i
英文摘要 .................................................................................................... ii
誌謝 .................................................................................................... iii
目錄 .................................................................................................... iv
表目錄 .................................................................................................... vi
圖目錄 .................................................................................................... vii

第一章、 序論............................................................................................ 1
1.1 研究動機.................................................................................... 1
1.2 論文組織........................................................... ........................ 2
第二章、 UWB研究背景............. .................. ..........................................
2.1 射頻系統架構之基本理論........................................................ 3
2.2 技術的運用...... ... .................................... ........... .................... 4
2.2.1 脈衝無線電觀念........................................................................ 4
2.2.2 多頻帶系統觀念........................................................................ 4
第三章、 低雜訊放大器架構.................. .................... ............................ 8
3.1 寬頻低雜訊放大器設計簡介.................................................... 8
3.2 低雜訊放大器(LNA)基本架構.................................................. 8
3.2.1 分佈式放大器電路架構(DA).. ................................................. 9
3.2.2 回授型放大器電路架構...... ...... .............................................. 10
3.2.3 電流再利用電路架構................ ............................................... 11
3.2.4 濾波器電路架構...... ...... ...... ............. ..................................... 13
3.2.5 共閘極電路架構...... ...... .................... ....... .... ... .................... 15
3.3 雜訊指數定義............................................................................ 16
3.3.1 電子元件雜訊來源....................................................................... 16
3.3.2 等效雜訊溫度............................................................................ 17
3.3.3 雜訊指數......... ....... .................................................................. 18
3.3.4 串接系統雜訊指數......... ....... .................................................. 18
3.4 非線性效應........... ........... ........ .... .......................................... 19
3.4.1 三階互調失真(IP3).................................................................... 19
3.4.2 增益壓縮點(P1dB)........................................................................ 20
3.5 穩定度..... .. .. ............................................................................ 21
第四章、 超寬頻低功率低雜訊放大器設計.............................. ....... ..... 23
4.1 架構簡介................................................................ ....... ....... ... 23
4.1.1 寬頻輸入匹配設計.............................................................. ..... 24
4.1.2 電流再利用電路架構................................................................ 25
4.1.3 參差協調技術....... ..... ..... ........................................................ 27
4.1.4 雜訊分析. ........ ........ ....... ........................................................ 29
4.2 電路設計........................................................ ........................... 29
4.2.1 設計流程........................................................................ ........... 30
4.3 電路佈局與模擬........................................................................ 32
4.3.1 電路佈局考量............................................................................ 32
4.3.2 模擬結果.................................................................................... 34
4.4 量測結果.................................................................................... 39
第五章、 超寬頻高增益低雜訊放大器設計.................................. .... .... 45
5.1 架構簡介................................................................ ....... ....... ... 45
5.1.1 共閘極輸入匹配設計................................................................ 46
5.1.2 高增益設計..................... . ...... ................................................. 48
5.2 電路設計與考量........................................................................ 48
5.2.1 設計流程.................................................................................... 49
5.3 前次下線量測結果與改善重點......................................…….. 51
5.4 電路重新佈局與模擬................................................................ 54
5.4.1 電路重新佈局考量.................................................................... 54
5.4.2 重新模擬結果............................................................................ 56
第六章、 結果與討論................................................................................ 63
第七章、 結論與未來展望........................................................................ 67
參考文獻 .................................................................................................... 68
附錄A 口試委員提問............................................................................ 70
作者簡介 .................................................................................................... 72

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