臺灣博碩士論文加值系統

本文針對傳輸/金氧半場效電晶體協力邏輯電路,做一詳細之分析暨應用 此特殊邏輯電路僅適用於低功率超大型積體電路,且為萬用閘 本文嘗試以此邏輯電路實現一組邏輯函數,探討傳輸電晶體衰減之訊號波形,以反相器改進還原此訊號,結果波形可還原至工作電壓,並可工作至高頻500百萬赫茲;本文亦嘗試以反相器閂鎖(latch)電路取代協力邏輯使用之邏輯準位還原電路,結果發現並不適用 最後不以二位元決策圖(BDD)演算法,而以直接對應傳統布林邏輯之[及][或]閘方式,對功率消耗大,證實對BDD演算法較佳 此外,以HSPICE模擬臨界路徑之訊號波形,而製程參數採聯華電子之0.5微米教育版,在高臨界電壓(Threshold Voltage, 0.8V)製程所得之延遲功率積亦可達到約金氧半場效電晶體邏輯的三分之一

This thesis focuses on the analysis and application of PCCL. The PCCL is especially used in low-power VLSI and a universal gate. We try to implement a set of logic functions and discuss the waveforms attenuated by pass-transistors. We discuss the technique improved by inverter-restoring and the waveform can be restored to at 500 MHz operation frequency. We try to replace the level-restoring circuit of PCCL by inverter-latch one. Finally, we don't implement by BDD, but implement by AND and OR gates of convWe simulate the critical-path waveform by HSPICE. The process parameters adopt the UMC 0.5 process for education. In the fixed process, The result of power-delay-product improves to nearly 1/3 compared with CMOS logic-style in high process.