臺灣博碩士論文加值系統

隨著科技的進步，半導體生產技術中的金氧半場效電晶體已從次微米的世代進入到28奈米或更小的世代，並依照摩爾定律(Moore’s law)的原則下，元件尺寸微縮是為了降低成本與增加積體電路中元件的密度之外，最主要的是提升元件的速度。近年來，許多學者提出應變工程技術，此應變工程(Strained engineering)技術應用在元件上，可以有效地改善元件電特性，而此技術中的應力可分為伸張應力(Tensile stress)與壓縮應力(Compressive stress)，或以結構上的設計造成雙軸應力(Biaxial stress)與單軸應力(Uniaxial stress)的局部性應力，來拉伸或壓縮晶格的結構以降低載子在通道中的質量或降低碰撞機會，使得載子遷移率(Mobility)可以提升。
此外，為了持續微縮互補式金氧半導體(CMOS)的尺寸，當通道長度縮短至45奈米後，在閘極製程上若還持續使用閘極氧化層為二氧化矽時其厚度將約為13Å或更小，這將會發生嚴重的載子穿隧現象，造成閘極可觀的漏電並造成IC整體電量的消耗，並隨著電晶體的尺寸微縮至奈米等級時，也有可能會產生嚴重的短通道效應與達到物理微縮的極限。因此透過高介電常數(High-k, HK)層與金屬閘極(Metal gate, MG)技術有機會來抑制元件尺寸微縮後的不良效應。
但High-k材料與通道表面常有不良的表面鍵結，雖可形成一層薄的二氧化矽介面層以資緩衝，但不一定能完全獲得保護。在此研究中將探討在HK/MG製程下再加上n/pMOSFETs有不同的應變製程組合時，瞭解電晶體元件之源/汲極接面品質與貫穿效應和元件通道長度大小的關連性，並用45奈米應變元件與之比較。

With the advancement of technology, the feature size of field-effect transistors coming from semiconductor manufacturing technology has evolved from sub-micron to 28nm process generation or beyond. Following the Moore's law, besides the reduction of process cost and the increase of device density in ICs due to the dimensional shrinkage of transistor devices, the increase of transistor switch speed is chiefly considered. Recently, many researchers proposed several strain engineering processes to promote the electrical characteristics of devices. In strain technology, there are two species: tensile strain and compressive strain. In the view of structural design, there are bi-axial strain (or global strain) and uni-axial strain (or local strain), causing tensile or compressive effect on device channel to improve the channel mobility. Because of these strain techniques, the effective mass or the probability of scattering for channel carriers will be reduced and the channel mobility will be relatively enhanced.
In addition, to continuously scale down the feature size of CMOS devices, the gate leakage due to direct tunneling effect is huge to degrade the IC performance if the gate dielectric is still silicon dioxide, especially at 45 nm process or beyond. At that time, the thickness of gate dielectric is around 13Å or below. The short channel effect will be more obvious and the physical limitation will be quickly approached. Through the incorporation of high-k and metal gate process technology has a chance to suppress these drawbacks due to device shrinkage.
However, there usually exists some bad bonding quality between high-k material and silicon channel surface. Forming a thin layer of interfacial layer as a buffer layer is a possible way to solve this interface issue, but may not be perfectly achieved. In this work, we focus on the S/D junction integrity with HK/MG process and the punch-through effect with the combination of strain technology or channel size variation. Furthermore, some strained devices under 45nm process will be treated as a control group to probe the shift among these devices under test.

目錄
摘 要 I
Abstract II
誌 謝 IV
目錄 V
表目錄 VII
圖目錄 VIII
第一章 緒論 1
1-1 簡介 1
1-2研究動機 2
1-3論文整體架構 2
第二章 文獻回顧 3
2-1 半導體材料 3
2-2 能帶與能隙 4
2-3載子的傳輸方式 7
2-4 p-n接面 12
2-4-1 空乏區寬度 13
2-4-2 空間電荷 14
2-5 MOSFET 元件物理特性 18
2-6 MOSFET 能帶圖 20
2-6-1 聚集效應 21
2-6-2 空乏效應 22
2-6-3 反轉效應 23
2-7 MOSFET 元件輸出特性 25
2-7-1 截止區 25
2-7-2 線性區 26
2-7-3 飽和區 27
2-8 MOSFET 元件轉移特性 28
2-9 MOSFET 其他重要元件之參數 30
2-9-1 次臨界特性 30
2-9-2 臨界電壓特性 32
2-9-3 遷移率退化 33
2-10 MOSFET 短通道效應 34
2-10-1 通道長度調變 34
2-10-2 速度飽和 36
2-10-3 臨界電壓下滑 37
2-10-4 汲極引起的位能下降 39
2-10-5 貫穿 40
2-11高介電係數材料與製程整合 42
2-11-1 高介電係數介電層 42
2-11-1-1 氧化鋁薄膜 43
2-11-1-2 氧化鋯薄膜 43
2-11-1-3 氧化鉿薄膜 44
2-11-1-4 氧化鑭薄膜 44
2-11-2 應變矽元件 45
2-11-2-1 應變矽特性表現 45
2-11-2-2 全面應變矽元件 46
2-11-2-3 局部應變矽元件 48
2-11-2-4 應變矽面臨之問題 51
第三章 實驗流程與方法 52
3-1 整體實驗架構及說明 52
3-2 元件結構介紹 53
3-2-1 High-K/Metal Gate製程流程 53
3-2-2 應變矽製程流程 55
3-3 八吋半導體手動探針量測平台 57
3-4 半導體特性系統(Keithley C4200) 58
3-5 實驗方法 60
3-5-1 ID-VD 特性曲線 60
3-5-2 ID-VG 特性曲線 60
3-5-3 接面崩潰特性曲線 60
3-5-4 貫穿效應特性曲線 61
第四章 實驗結果與討論 62
4-1第一階段實驗結果 62
4-2第二階段實驗結果 71
第五章 結論 81
參考文獻 82

參考文獻
[1]Weiying Gu, et al., “Strained silicon dynamic threshold voltage MOSFETs for low voltage and ultra-high speed CMOS circuits,” International Conference on Solid-State and Integrated-Circuit Technology, pp. 134 - 137, Oct. 2008.
[2]Yazdani, K.E, et al. “Ballistic phonon transport in strained Si/SiGe nanostructures with an application to strained-silicon transistor”, The Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, Vol.2, pp. 424- 430, 1-4 June 2004.
[3]Thompson S.E, et al. “A 90-nm logic technology featuring strained-silicon”, IEEE Transactions on Electron Devices, vol. 51, no. 11, pp. 1790- 1797, 25 October 2004.
[4]Mazure C, et al., “Status of device mobility enhancement through strained silicon engineering,” IEEE International SOI Conference, October3-6,2005
[5]Misra, D, et al., “Interface engineering of high-K and high-mobility substrate interface,” IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Nov. 1, pp. 1-4, Oct. 29 2012
[6]Hsin-Chia Yang, et al., “Study of temperature effects of mobility, swing, and early voltages on strained MOSFET devices,” 2011 IEEE 4th International Nanoelectronics Conference (INEC), pp.1-2, 21-24, Jun. 2011.
[7]McMahon, W, et al., “Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process,” IEEE International Reliability Physics Symposium (IRPS), pp. 4C.4.1 - 4C.4.4 , 14-18 April 2013.
[8]Lin, P.Y, et al., “Self-align nitride based logic NVM in 28nm high-k metal gate CMOS technology,” International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), pp.1-2, 21-24, 22-24 April 2013
[9]Kasim, R, et al., “Reliability for manufacturing on 45nm logic technology with high-k + metal gate transistors and Pb-free packaging,” IEEE International Reliability Physics Symposium, pp. 350-354, April 2009.
[10]施敏，“半導體元件物理與製作技術”，國立交通大學出版社，2002 年。
[11]Chenming Hu, “Modern Semiconductor Devices For Integrated Circuits”, 台灣培生教育出版股份有限公司，Taiwan，2010
[12]S.M. Sze, “Semiconductor Devices Physics and Technology,” John Wiley & Sons Inc , May, 2012.
[13]Kawaguchi, H, et al., “A Robust 0.15/spl mu/m CMOS technology With CoSi/sub 2/ Salicide And Shallow Trench Isolation, ” Symposium on VLSI Technology, pp. 125-126, 1997
[14]J.P. Colinge, “Subthreshold slope of thin-film SOI MOSFET's,” IEEE Electron Device Letters, Vol. 7, No. 4, pp. 244-246, 1986.
[15]J.P. Colinge, J.W. Park, W. Xiong, “Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs,” IEEE Electron Device Letters, Vol. 24, No. 8, pp. 515-517, 2003.
[16]D.M. Caughey, et al., “Carrier Mobility in Silicon Empirically Related to Doping and Field , ” IEEE Proceedings, Vol. 855, no.12, pp. 2192-2193, Dec. 1967.
[17]劉傳璽，“半導體元件物理與製程” ，五南圖書出版，2011年。
[18]Robertson, J, et al., “Electronic structure and band offsets in high K oxides, ” Extended Abstracts of International Workshop on Gate Insulator, pp. 71-72, 1-2 Nov. 2001
[19]Wilk, G.D, et al., “High-κ gate dielectrics: Current status and materials properties considerations,” Journal of Applied Physics, Vol. 89, no.10, May 2001.
[20]Robertson, J, et al., “Band offsets of wide-band-gap oxides and implications for future electronic devices,” J. Vac. Sci. Technol. Vol. 18, pp. 1785-1791, 2000.
[21]Spahr, H, et al., “Regimes of leakage current in ALD-processed Al2O3 thin-film layers,” Journal of Physics D: Applied Physics, Vol. 46, No. 15, 2013.
[22]Seungho Lee, et al., “Characteristics of an Al2O3 Thin Film Deposited by a Plasma Enhanced Atomic Layer Deposition Method Using N2O Plasma,” Electronic Materials Letters, Vol. 3, No. 1, pp. 17-21, 2007.
[23]陳立民，成功大學，奈米微晶二氧化鋯作為閘極氧化層之製備與特性研究，2004.
[24]Garros, Xpp, et al., “Investigation of HfO2 dielectric stacks deposited by ALD with a Mercury Probe,” Proceeding of the 32nd European Solid-State Device Research Conference, pp. 411-414, 24-26 September 2002.
[25]Zhu, W.J, et al., “Effect of Al inclusion in HfO2 on the physical and electrical properties of the dielectrics,” IEEE Electron Device Letters, Vol. 23, No. 11, Nov. 2002.
[26]Dong Hak Kim, et al., “Effect of Thermal Annealing on Nonvolatile Memory Structures Containing a high-k La2O3 Charge-trapping Layer,” Vol. 58, No. 2, pp. 264-269, February 2011.
[27]林宏年、呂嘉裕、林鴻志、黃調元，“局部與全面形變矽通道(Strained Si channel)
互補式金氧半(CMOS)之材料、製程與元件特性分析(I) ”，奈米通訊，第 十二卷第一、二期，2005 年。
[28]Koganemaru, M., et al., “Device Simulation for Evaluating Effects of Inplane Biaxial Mechanical Stress on n-Type Silicon Semiconductor Devices,” IEEE Transactions on Electron Devices, Vol. 58, No. 8, pp. 2525 – 2536, Aug. 2011.
[29]Yang, Peizhen, et al., “Mechanism for improvement of n-channel metal-oxide-semiconductor transistors by tensile stress,” Journal of Applied Physics, Vol. 108, No. 3, pp. 034506 - 034506-12, Aug 2010.
[30]Wang, J.G, et al., “Origin of tensile stress in the Si substrate induced by TiN/HfO2 metal gate/high-k dielectric gate stack,” Applied Physics Letters, Vol. 93, No.16, pp. 161913 - 161913-3, Oct 2008.
[31]Li Xuying, et al., “Analysis of stress relaxation and data acquisition in the Compression Process of Herbage Materials,” International Conference on Mechanic Automation and Control Engineering (MACE), pp. 5892 - 5895, 26-28 June 2010.
[32]C. H. Chen, et al., “Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application,” IEEE VLSI Technology, pp.56-57, June 2004.
[33]Kang, C.Y., et al., “Effects of thin SiN interface layer on transient I-V characteristics and stress induced degradation of high-k dielectrics,” IEEE International Reliability Physics Symposium Proceedings, pp.587-588, 25-29 April 2004.
[34]Weber, O, et al., “Examination of Additive Mobility Enhancements for Uniaxial Stress Combined with Biaxially Strained Si, Biaxially Strained SiGe and Ge Channel MOSFETs,” IEEE International Electron Devices Meeting, pp. 719 – 722, 10-12 Dec. 2007.
[35]Keepek K., et al., “High-mobility substrate-si PMOSFETs,” IEEE Electron Devices, Vol. 43, pp. 1709 – 1716, Oct. 1996.
[36]Mizuno, Tomohisa., et al., “Advanced SOI p-MOSFETs with strained-Si channel on SiGe-on-insulator substrate fabricated by SIMOX technology,” IEEE Electron Devices, Vol. 48, pp. 1612 – 1716, Oct. 1996.
[37]林宏年、呂嘉裕、林鴻志、黃調元，“局部與全面形變矽通道(Strained Si channel)
互補式金氧半 (CMOS)之材料、製程與元件特性分析(II) ”，奈米通訊，第 十二卷第一、二期，2005 年。
[38]維基百科http://zh.wikipedia.org/wiki/Wikipedia:%E9%A6%96%E9%A1%B5.