臺灣博碩士論文加值系統

本篇論文將介紹一個全數位時脈資料回復電路。由於擁有將回復時脈重新對準資料的特性，此時脈資料回復電路可用於回復以突發模式傳送的資料。由於其回復資料的方式為半速率，所以回復時脈的頻率僅需資料位元率的一半。採用全數位的型式，振盪器的輸出時脈頻率是由二進位的控制碼來控制，先採用時間至數位轉換器進行高位元粗調，再經由一個上/下數計數器來進行週期時間微調，以達到控制頻率的效果。本電路實現了微調機制，為其他能夠重新對準回復時脈並接收突發模式資料的時脈資料回復電路所沒有的功能，此機制可以修正參考時脈的誤差。

此時脈回復電路操作在定速625 Mb/s的位元率下，其回復時脈與回復資料之抖動分別為345ps(於312.5MHz時)與250ps (於625 Mb/s位元率時)，功率消耗在供給電壓為1.8伏特時為8mW，且全電路將由0.18-μm CMOS製程實現。

This thesis presents the work of an all-digital half-rate burst-mode clock and data recovery circuit (CDR). Since it possesses the capability of realigning the recovered clock from the input data, this clock and data recovery circuit can be used to retiming the data which transmit under burst-mode. It can operate at the half-rate mode, so the frequency of recovered clock can be only half of the bit rate of data. With the aid of the all-digital mechanism, the frequency of the oscillator is controlled by a set of binary codes. The MSB of this binary code is derived from the Time-to-Digital Converter, and then the LSB is counted by an up/down counter for fine adjustment. This circuit achieves the function of fine control which hasn’t accomplished in many other clock and data recovery circuit with the ability to realign the recovered clock from the burst-mode data. This function can correct the frequency deviation which is caused by reference clock.

For this clock and data recovery circuit, it operates at 625Mb/s bit rate. The jitter of the recovered clock and retimed data are 345ps (clock frequency @312.5MHz) and 250ps(data bit rate @625Mb/s), respectively. The power consumption is 8mW under a 1.8-V power supply voltage, and it will be implemented by 0.18-μm CMOS process.

中文摘要 i

ABSTRACT ii

誌謝 iii

目錄 iv

表目錄 vii

圖目錄 viii

第一章 緒論 1

第二章 時脈資料回復電路簡介 3

2.1延遲鎖定迴路 3

2.1.1數位延遲鎖定迴路 6

2.2歸零訊號與不歸零訊號 6

2.3時脈資料回復電路架構簡介 7

2.4回復資料的決策電路 9

2.4.1全速率資料回復 9

2.4.2半速率資料回復 11

2.4.3四分之一速率回復資料 12

第三章 全數位突發模式時脈資料回復電路 14

3.1系統需求 14

3.1.1系統架構 14

3.2參考時脈的檢測 15

3.2.1使用時間至數位轉換器檢測參考時脈的週期 16

3.2.2設計實際考量 20

3.3回復時脈的重新對準 23

3.3.1突發模式訊號 23

3.3.2資料上升邊緣的檢測 25

3.4回復時脈的產生 28

3.4.1重新對準振盪器 28

3.4.2考量設計需求的另一種重新對準振盪器型態 30

3.4.3數位控制重新對準振盪器 31

3.5資料的回復 35

3.5.1時間至數位轉換器與數位控制延遲線之關係 35

3.5.2回復時脈之延遲相位 37

3.5.3回復時脈週期的檢測 38

3.5.4回復時脈週期檢測器 42

3.5.5完整架構 44

第四章 電路模擬 46

4.1上升邊緣檢測器模擬 46

4.2回復時脈週期檢測模擬 48

4.3參考時脈週期檢測模擬 48

4.4數位控制重新對準振盪器效能 49

4.5資料回復模擬 50

4.5.1規律資料下的功能驗證 51

4.5.2亂數資料下的功能驗證 55

4.5.3 回復時脈與回復資料的Glitch現象 66

4.6 電路性能總結 67

第五章 總結 69

參考文獻 70

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