臺灣博碩士論文加值系統

摘 要

迴旋碼的解碼法則中，以最大相似解碼法則---腓特比演算法為公認的有效率之近似解碼演算法。本文主要是針對數位電視地面廣播系統中所訂定的間空迴旋碼，希望設計實現出一個符合系統解碼速度的腓特比解碼器，且研究於軟判決的解碼方式，以希望提升錯誤保護之能力。
軟判決解法方式，是依照最大相似解碼法則衍生出最小距離法則，再按照量化位階的不同給予不同的分支路徑計量値，本論文內分析比較硬判決以及軟判決量化位階為Q=8、Q=16的效能，且提供硬體實現上，參數設定的依據。硬體實現上，比較不同的實作方式，採用全平行的架構，為了能夠更加快速度且節省資源，使用模數歸一的正規化方式；最後，以較簡單的3-指標偶數區塊追溯法來完成整個解碼器。在計算分支路徑計量値時，使用量化位階為Q=16的方式。

ABSTRACT

Viterbi algorithm is the well-known and efficiently maximum likelihood decoding algorithm applied to decode convolutional code. In this discussion, it concentrates on the standard of punctured convolutional
encoder in DVB-T system. To design and implement a Viterbi decoder agreed with the decoding throughput which limited by the system, on the other hand, to research the soft-decision method for decoding process with the result in promoting the bit error rate！
The way used to soft-decision is by the minimum distance algorithm
. Bit branch metrics have different value if the quantized level is not the same for soft-decision decoding. The analysis is focusing on the performance of soft-decision quantized level Q=8 and Q=16 and hard-dec
ision and a basis for the coming IC design of Viterbi decoder. In the implementation issue, full parallel architecture and modulo normalization
are used to save the source and decoding throughput, then the 3-pinter even block method is used to trace back and decoding the data.
At the last, we implement the Viterbi decoder by above-mentioned ways and the soft-decision quantized level is Q=16.

目 錄


頁次
中文摘要………………………………………………………………..…….I
英文摘要………………………………………………………………..…... II
致謝………………………………………………………………….............. III
目錄…………………………………………………………………….….. IV
圖目錄……………………………………………………………………….. VI
表目錄……………………………………………………………….…XI


第一章 緒論…………………………………………………………………..1
1.1 研究動機與背景……………………………………………………..1
1.2 研究方法與目的……………………………………………………..2
1.3 章節編排.……………………………………………………………..2
第二章 歐規數位電視地面廣播(DVB-T)之錯誤更正碼技術…………..4
2.1 數位電視地面廣播系統簡介………………………………………..4
2.2 通道編碼技術………………………………………...……………10
2.2.1 外部編碼器(Outer Coder)………..…..……………………11
2.2.2 外部交錯器(Outer Interleaver)……………………………12
2.2.3 內部編碼器(Inner Coder)…..………………………………13
2.2.3.1 (2,1;6)迴旋碼(Convoltional Encoder)…………..13
2.2.3.2 間空程序(Punctured Process).…………………14
2.2.4 內部交錯器(Inner Interleaver)......……………………...15
2.2.4.1 位元交錯器(Bit-Wise Interleaver)…….…..………16
2.2.4.2 符號交錯器(Symbol-Wise Interleaver)….....………18
第三章 迴旋碼與Viterbi 解碼演算法…..…………………………………20
3.1 迴旋碼…………….………………………………………………20
3.1.1 迴旋碼的定義……………………………………………….20
3.1.2 迴旋碼的結構與特性………........………...….…………….23
3.2 最大相似解碼演算法…….…………………………………………25
3.2.1 腓特比(Viterbi)解碼演算法..………..……………………25
3.2.2 腓特比(Viterbi)解碼範例……..…………………………….26
3.3 軟判決(Soft Decision)腓特比解碼技術…………..…………….31
3.3.1 位元分支路徑計量値計算…...………..……………………31
3.3.2 量化位元數模擬分析…….……..…………………………38
第四章 腓特比(Viterbi)解碼器設計…..……………………………….....42
4.1 腓特比(Viterbi)解碼器基本架構與分類…….……….…………42
4.2 腓特比(Viterbi)解碼器硬體實現策略....…….……….…………44
4.2.1 分支路徑計值單元 (BMU)………………………………44
4.2.2 加-比較-選擇單元 (ACSU)………………………………46
4.2.3 累積路徑計量值記憶體單元 (PMMU)……………………48
4.2.4 存活記憶體單元 (SMU)…….……………………………49
4.3 腓特比(Viterbi)解碼器架構規劃......……….……….…………52
4.3.1 分支路徑計值單元規劃…..………………………………53
4.3.2 加-比較-選擇單元規劃………..…………………………55
4.3.3 存活記憶體單元規劃……….………….…………………58
第五章 腓特比(Viterbi)解碼器模擬與電路合成…...………………….....68
第六章 結論與未來發展………………………………………………80
參考文獻………………………………………………………………81
簡歷……………………………………………………………………84

參 考 文 獻

1.ESTI, “Digital Video Broadcasting (DVB); Framing Structure, Channel Coding and Modulation for Digital Terrestrial Television”, European Telecommunication Standard EN300744 v1.4.1, 2001
2.Horvath, L.; Dhaou, I.B.; Tenhunen, H.; Isoaho, J.,”A novel, high-speed, reconfigurable demapper-symbol deinterleaver architecture for DVB-T”, Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium onVolume 4, 30 May-2 June 1999 Page(s):382 - 385 vol.4.
3.Yong Wang; Jian Hua Ge; Bo Ai; Pei Liu; ShiYong Yang,”A soft decision decoding scheme for wireless COFDM with application to DVB-T”. Consumer Electronics, IEEE Transactions onVolume 50, Issue 1, Feb 2004 Page(s):84 - 88
4.Kyu-Man Lee; Dong-Seong Han; Ki-Bum Kim,“Performance of the Viterbi decoder for DVB-T in Rayleigh fading channels”, Consumer Electronics, IEEE Transactions on Volume 44, Issue 3, Aug. 1998 Page(s):994 – 1000.
5.Min-Young Park; Weon-Cheol Lee; Jong-Ho Kwak; Choul-Hee Cho; Hyung-Mo Park,” A demapping method using the pilots in COFDM system” Consumer Electronics, IEEE Transactions on Volume 44, Issue 3, Aug. 1998 Page(s):1150 – 1153.
6.李果穎(Josh Lee),”Bit Error Ratio in DVB as a Function of S/N”,台灣羅德史瓦茲有限公司,Rohde & Schwarz Taiwan Ltd.
7.Lou, H.-L,”Implementing the Viterbi algorithm”, Signal Processing Magazine, IEEE Volume 12, Issue 5, Sept. 1995 Page(s):42 – 52

8.Biver, M.; Kaeslin, H.; Tommasini, C.,”In-place updating of path metrics in Viterbi decoders”, Solid-State Circuits, IEEE Journal ofVolume 24, Issue 4, Aug. 1989 Page(s):1158 – 1160.
9.Ming-Der Shieh; Ming-Hwa Sheu; Chien-Ming Wu; Wann-Shyang Ju,”Efficient management of in-place path metric update and its implementation for Viterbi decoders”, Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium onVolume 4, 31 May-3 June 1998 Page(s):449 - 452 vol.4.
10.Chien-Ming Wu; Ming-Der Shieh; Chien-Hsing Wu; Ming-Hwa Sheu,”An efficient approach for in-place scheduling of path metric update in Viterbi decoders”, Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on Volume 3, 28-31 May 2000 Page(s):61 - 64 vol.3.
11.Chien-Ming Wu; Ming-Der Shieh; Chien-Hsing Wu; Ming-Hwa Sheu,” VLSI architecture of extended in-place path metric update for Viterbi decoders”, Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on Volume 4, 6-9 May 2001 Page(s):206 - 209 vol. 4.
12.Shung, C.B.; Siegel, P.H.; Ungerboeck, G.; Thapar, H.K,”VLSI architectures for metric normalization in the Viterbi algorithm”, Communications, 1990. ICC 90, Including Supercomm Technical Sessions. SUPERCOMM/ICC '90. Conference Record., IEEE International Conference on 16-19 April 1990 Page(s):1723 - 1728 vol.4.
13.Black, P.J.; Meng, T.H.-Y,”Hybrid survivor path architectures for Viterbi decoders”, Acoustics, Speech, and Signal Processing, 1993. ICASSP-93.,

1993 IEEE International Conference on Volume 1, 27-30 April 1993
Page(s):433 - 436 vol.1.
14.Feygin, G.; Gulak, P, ”Architectural tradeoffs for survivor sequence memory management in Viterbi decoders”, Communications, IEEE Transactions on Volume 41, Issue 3, March 1993 Page(s):425 – 429.
15.Jae-Sun Han; Tae-Jin Kim; Chanho Lee, ”High performance Viterbi decoder using modified register exchange methods”, Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Volume 3, 23-26 May 2004 Page(s):III - 553-6 Vol.3.
16.Onyszchuk, I.M, “Truncation length for Viterbi decoding”, Communications, IEEE Transactions on Volume 39, Issue 7, July 1991 Page(s):1023 – 1026.
17.Black, P.J.; Meng, T.H,” A 140-Mb/s, 32-state, radix-4 Viterbi decoder”, Solid-State Circuits, IEEE Journal of Volume 27, Issue 12, Dec. 1992 Page(s):1877 – 1885.
18.Xilinx,”Viterbi Decoder v5.0”,Product Specification.
http://www.xilinx.com , 2004
19.周良昌,”適用於無線區域網路802.11a之Viterbi解碼器硬體實現”, 中華大學電機工程學系碩士論文,2003.