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Abstract (Chinese) IV
Abstract (English) VI
Acknowledgement VIII
Contents IX
Table Captions XII
Figure Captions XIII
Chapter 1 Introduction
1.1 Background and Motivation 1
1.1.1 Application of Strain Technology to Enhance Device Performance with Gate Engineering 2
1.1.2 Development of High-k/Metal Gate Structure 3
1.2 Charge Pumping Detection of High-k/Metal Gate Profile 4
1.3 Organization of this Dissertation 6
Chapter 2 The Impact of Ultimate Spacer process and Notch Gate Structure on Poly Gate CMOS Performances
2.1 Improvement of 45 nm and Beyond CMOSFETs Performances with Ultimate Spacer Process 15
2.1.1 Device Enhancement Technology 15
2.1.2 FUSI-USP Process 16
2.1.3 Effect of Ultimate Spacer Process on N/PMOS Performances 16
2.1.4 Summary 17
2.2 Use of the Novel Gate Structure to improve 45 nm and Beyond CMOSFETs Performances 22
2.2.1 CESL Stress Impact on Device Performance 22
2.2.2 Notch Gate Process 22
2.2.3 Strain Engineer Enhancement with Notch Gate Structure 23
2.2.4 Summary 25
Chapter 3 Threshold Voltage Adjustment and Reliability Analysis for High-k/Metal Gate Device
3.1 Effect of Nitrogen Incorporation in Gd Cap Layer of Hf-Based High-k/Metal Gate nMOSFETs 35
3.1.1 Brief of High-k/Metal Gate 35
3.1.2 High-k/Metal Gate Process 36
3.1.3 Work Function Tuning and Reliability Inspection 38
3.1.4 Summary 40
3.2 Improvement of TDDB Reliability of HfO2 High-k/Metal Gate MOSFET Device with Oxygen Post Deposition Annealing 45
3.2.1 Brief of High-k Reliability 45
3.2.2 Oxygen Post Deposition Annealing Process 45
3.2.3 TDDB, PBTI and NBTI Reliability Analyses 46
3.2.4 Summary 48
Chapter 4 Improvement of High-k/Metal gate pMOSFETs Performance and Reliability with SiGe channel Structure
4.1 Introduction of SiGe Channel 60
4.2 SiGe Process 61
4.3 Enhancement by Optimism Si Cap/SiGe channel Structure 61
4.4 Summary 63
Chapter 5 Impact of Interfacial Layer on Performance of 28 nm Gate-First and Gate-Last High-k/Metal gate CMOSFET
5.1 VFB Roll Off Issue 76
5.2 Experiment Details 77
5.3 Comparison between Gate First and Gate Last Device 77
5.4 Summary 80
Chapter 6 Conclusion and Prospect
6.1 Conclusion 99
6.2 Prospect 100
References 102
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