臺灣博碩士論文加值系統

由於IC製程不斷地進步，電晶體尺寸的縮小，各種通道造成的效應，電壓下降、製造和溫度造成的偏移，使得電路設計越來越困難；而電路設計在系統整合上，電路與電路之間的訊號同步是非常重要的一部份，故如何解決訊號之間的同步是我們當下的目標。
延遲鎖定迴路主要是作用在不同電路之間的時脈訊號同步與追蹤，也因為容易設計、穩定、低功耗的特性，使得延遲鎖定迴路廣為使用在電路系統或電路與電路之間同步的訊號。本篇論文主要是利用別的方法來改善延遲鎖定迴路的相位誤差，使訊號達到同步的改善。由於延遲鎖定迴路在回授後，因為充電泵有著不匹配的問題，使得輸入與輸出的相位有著相位差。所以我們打算運用計數器來尋找D型正反器的setup time進行校正，改善輸入與輸出之間的相位。
在我們設計的電路架構中，是使用0.18微米 CMOS製程來製作出整體電路系統，而晶片面積1*1 mm^2，輸入參考頻率為700~900MHz，電源供應電壓為1.8伏特時，整體電能消耗功率為46mW。其中，當輸入頻率在900MHz時，輸入與輸出的相位誤差為3.3ps，抖動峰對峰值為14ps。

Because of the development of technology, smaller scale of MOSFET, channel effect, low supply voltage, and process-voltage-temperature variations, circuit design has become more and more difficult. The synchronous problem between circuits is undoubtedly important in system integration.
Delay-locked loop is designed and implemented to solve the problem of clock synchronization and tracking. Delay-locked loop is widely used because of easy design, stability, and low power consumption. This thesis presents a new method to improve DLL’s phase error. Due to the current mismatch of Charge Pump, the input and output have phase error. We use the D flip-flop’s setup time to reduce current mismatch of Charge Pump in DLL.
This chip is implemented in a 0.18μm CMOS process with 1.8V power supply voltage. The total area of the chip is 1*1mm2. The operating frequency range is from 700MHz to 900MHz. The power consumption is 46mW. The phase error is 3.3ps and peak-to-peak jitter is 14ps at 900MHz.

指導教授推薦書.................................................................................i
口試委員會審定書.............................................................................ii
授權書................................................................................................. iii
誌謝.....................................................................................................iv
中文摘要............................................................................................. v
英文摘要............................................................................................. vi
目錄..................................................................................................... vii
圖目錄.................................................................................................x
表目錄.................................................................................................xiv
第一章 簡介.......................................................................................1
1.1 研究動機及應用................................................................1
1.2 論文概要............................................................................3
第二章 延遲鎖定迴路基本架構與介紹……...................................5
2.1 延遲鎖定迴路架構簡介...................................................5
2.2 延遲鎖定迴路基本方塊介紹...........................................7
2.3 延遲鎖定迴路系統分析...................................................12
第三章 相關文獻討論……….......................…................................16
3.1 改善相位誤差的校正方法與設計.................................. 16
第四章 延遲鎖定迴路問題分析與設計考量................................... 24
4.1 鎖定範圍.......................................................................... 24
4.2 啟動控制電路….............................................................. 27
4.3 相位頻率偵測器..............................................................29
4.4 充電泵..............................................................................32
4.5 電壓控制延遲線.............................................................. 37
第五章 電路實現與設計................................................................... 41
5.1 具有相位誤差校正之延遲鎖定迴路.............................. 41
5.2 具有相位誤差校正之延遲鎖定迴路子電路介紹..........45
5.3 MATLAB® Behavior Simulation.....................................57
5.4 HSPICE® Simulation........................................................69
第六章 電路佈局與晶片量測...........................................................75
6.1 晶片量測與環境設置......................................................75
6.2 具有相位誤差校正之延遲鎖定迴路量測......................77
6.3 晶片訊號量測..................................................................78
6.4 晶片量測結果比較..........................................................85
6.5 電路設計規格與相關文獻比較......................................88
第七章 結論及未來研究方向...........................................................89
7.1 結論..................................................................................89
7.2 未來改進方向...................................................................90
參考文獻..............................................................................................91



圖 目 錄
圖2.1.1 典型延遲鎖定迴路方塊圖.................................................. 6
圖2.2.1相位偵測器........................................................................... 7
圖2.2.2相位頻率偵測器................................................................... 9
圖2.2.3相位頻率偵測器、充電泵和迴路濾波器結合電路模型..10
圖2.2.4電壓控制延遲線..................................................................12
圖2.3.1延遲鎖定迴路線性模型......................................................13
圖3.1推挽式的充電泵架構.............................................................17
圖3.2含運算放大器的充電泵架構.................................................18
圖3.3改善漏電流的充電泵架構.....................................................19
圖3.4電壓電流轉換的充電泵.........................................................20
圖3.5控制延遲開關的相位頻率偵測器.........................................21
圖4.1.1輸入與輸出在相位偵測器的比較點..................................25
圖4.1.2陷入鎖定..............................................................................26
圖4.2.1啟動控制..............................................................................28
圖4.3.1相位頻率偵測器特性曲線..................................................30
圖4.3.2 以NAND為基礎的相位頻率偵測器................................30
圖4.3.3相位頻率偵測器..................................................................31
圖4.4.1電荷分享效應......................................................................32
圖4.4.2基本電流鏡.........................................................................33
圖4.4.3開關在汲極、閘極、源極的充電泵.................................35
圖4.4.4運用運算放大器的充電泵.................................................36
圖4.4.5只用NMOS當開關的單端充電泵...................................36
圖4.5.1 RC時間常數控制之延遲元件...........................................37
圖4.5.2餓電流控制之延遲元件.....................................................38
圖4.5.3差動對稱性負載之延遲元件.............................................39
圖4.5.4對稱性負載之IV特性.......................................................40
圖5.1.1具有相位誤差校正之延遲鎖定迴路架構圖.....................41
圖5.1.2電路時序圖.........................................................................44
圖5.2.1啟動控制電路.....................................................................46
圖5.2.2相位頻率偵測器.................................................................47
圖5.2.3鎖定偵測器.........................................................................48
圖5.2.4充電泵電路圖.....................................................................50
圖5.2.5 14級電壓控制延遲線.......................................................52
圖5.2.6 D型正反器的特性.............................................................54
圖5.2.7校正電路.............................................................................56
圖5.3.1 設計流程圖 ....................................................................... 57
圖5.3.2 MATLAB Simulink 的延遲鎖定迴路...............................58
圖5.3.3電壓控制延遲線控制電壓VC............................................58
圖5.3.4啟動控制電路.......................................................................59
圖5.3.5經過啟動控制電路後時序圖...............................................59
圖5.3.6相位頻率偵測器...................................................................60
圖5.3.7充電泵...................................................................................60
圖5.3.8電壓控制延遲線...................................................................61
圖5.3.9偵測電路...............................................................................61
圖5.3.10 5bits延遲開關....................................................................62
圖5.3.11 5bits D型閂鎖器................................................................62
圖5.3.12 5bits 上數/下數二進制計數器..........................................62
圖5.3.13校正電路.............................................................................63
圖5.3.14 VC電壓與DFF setup time.................................................65
圖5.3.15時序圖.................................................................................66
圖5.3.16頻率為700MHz時VC電壓.............................................67
圖5.3.17頻率為800MHz時VC電壓.............................................67
圖5.3.18頻率為900MHz時VC電壓.............................................68
圖5.4.1 HSPICE模擬延遲鎖定迴路在製程變異參數TT條件下.........................................................................................................70

圖5.4.2 HSPICE模擬延遲鎖定迴路在製程變異參數SS條件下......................................................................................................71
圖5.4.3 HSPICE模擬延遲鎖定迴路在製程變異參數FF條件下......................................................................................................72
圖6.1.1 量測晶片訊號輸出考量...................................................75
圖6.1.2 量測環境設備.................................................................. 76
圖6.2.1 晶片布局影像圖.............................................................. 77
圖6.2.2核心晶片佈局....................................................................77
圖6.3.1參考頻率700MHz相位誤差量測................................... 79
圖6.3.2參考頻率700MHz相位抖動量測................................... 80
圖6.3.3參考頻率800MHz相位誤差量測................................... 81
圖6.3.4參考頻率800MHz相位抖動量測................................... 82
圖6.3.5參考頻率900MHz相位誤差量測................................... 84
圖6.3.6參考頻率900MHz相位抖動量測................................... 85





表 目 錄
表5.3.1在不同頻率下的頻寬及鎖定時間表...................................66
表5.4.1在TT製程下，溫度、電壓相同，模擬不同輸入參考頻率並比較輸出與輸入訊號的比較表.............................................................73
表5.4.2在SS製程下，溫度、電壓相同，模擬不同輸入參考頻率並比較輸出與輸入訊號的比較表.............................................................74
表5.4.3在FF製程下，溫度、電壓相同，模擬不同輸入參考頻率並比較輸出與輸入訊號的比較表.............................................................74
表6.4.1 相位誤差量測比較表..........................................................86
表6.4.2 相位抖動峰對峰值量測比較表..........................................86
表6.4.3相位抖動均方根值量測比較表...........................................87
表6.5.1 電路規格表..........................................................................88
表6.5.2 相關文獻比較表..................................................................88

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