臺灣博碩士論文加值系統

近年來，無線通訊的應用顯得越來越趨重要，且無線通訊常在我們日常生活中扮演著不可或缺的角色。無線產品的市場逐漸成長茁壯，而產品的需求量更是日以月增。因此，如何將商品微小化與降低成本，是我們所感興趣的首要研究方向。
這篇碩士論文將探討如何實現一具低電壓且小晶片面積的無線接收機，第三章裡面所描述的即是一單晶化，卻具備完整接收能力的接收機。此電路只需使用1.8V的供應電壓，僅消耗約7.2mW的功率。晶片面積若不包含PAD的話，僅佔長173.1um、寬186.9um的面積。射頻訊號的調變方式採用開關移鍵的方式，所以此接收機專門被設計來接收解調此種調變訊號。經由實驗結果我們得知此接收機在訊號載波433MHz頻率下的接收靈敏度為 - 61dBm，其接收的訊號強度動態範圍則為44dB。訊號最大可接收的資料速度可高達6Mbps。由於具備微小化與低耗電的優點，此電路很適合用來放入系統晶片內整合，以達成無線生醫感測網路等應用。
另外一項電路技術稱作訊號強度偵測的功能也被實現且和之前所討論的開關移鍵接收機整合在一起。在最小的功率消耗考量下，此電路架構採用七級放大偵測功能達成。每一放大單元採用電流可重複使用的架構而非一般較耗能且不適合低電壓的方式。因此，除了可接收解調開關鍵射頻訊號之外，還可以對其偵測訊號強度。此電路有效面積不包含PAD外僅佔0.115mm2 ,在2.5V電壓操作下功率消耗為36.75mW。
另外一方面，由於被動式RFID越趨成熟穩定，主動式RFID在市場上變成頗須迫切發展的目標。我們將設計一射頻前端電路與一現有業界標準8051的微控制器來搭配使用。此接收機的可接收頻寬介於800MHz和1GHz之間，涵蓋了一些主動式RFID常用的頻率如868MHz和915MHz等。

In recent years, the applications of wireless communication become more and more important. Wireless communication plays an essential role in our daily lives. The market of the wireless applications grows up gradually. The demands of the wireless products also increase rapidly. Therefore, the miniaturization and low costs will be the first topic we are interested in.
This thesis is going to discuss a low-voltage wireless receiver with small chip area. A fully monolithic receiver is implemented in chapter 3. The supply voltage is only 1.8V with the total power dissipation of 7.2mW. The die even just occupies 173.1um by 186.9um excluding pads. This receiver is one kind of ASK (Amplitude shift keying) receivers, called OOK (On-off shift keying) receiver, and it can receive OOK signals and demodulate them perfectly. The experimental results show that a sensitivity of –61dBm with a receiving power dynamic range of 44dB is achieved at 433MHz frequency band. The maximum data rate can be even up to 6Mbps. Because of miniaturization and low power consumption, this receiver is suitable to be integrated into a wireless integration chip such as an implantable biomedical wireless sensor network.
The circuit technique for the application of signal strength indicator is realized. A seven-stage amplifier architecture was derived under minimum power consideration. Each gain cell adopts current-reuse structure rather than the conventional diode load for low supply voltage. This circuit can also receiver the wireless OOK signal in addition to RSSI. The prototype occupies an active area of 0.115mm2 (W/O pad). It consumes 36.75mW from a 2.5V power supply.
On the other hand, due to the maturity of passive RFID, the development of active RFIC would become an urgent goal for the market. Therefore, we will design a RF front-end circuit with an existing microcontroller based on the industry-standard 8051 architecture. The UHF band is selected from 800MHz to 1GHz, which could cover the popular frequencies, 868MHz and 915MHz, for RFID products.

Chapter 1 Introduction …………………………………………......1
1.1 Motivation ………………………………………………………………………....1
1.2 Thesis Organization ………………………………………………………………3
Chapter 2 Receiver Architectures ………………...………..………...5
2.1 Introduction …..………………………………………………………………..5
2.2 Common Receiver Architectures …...………………………………………….7
2.2.1 Introduction .……...………………………………………………………7
2.2.2 Heterodyne Receivers ……………………………………………………8
2.2.3 Homodyne Receivers………………………………………....…………….14
2.3 Summary………………………………………………………………………….19
Chapter 3 A Monolithic OOK Receiver for Wireless Sensor
Network ….…………………………………...………...23
3.1 Introduction ..……………..……………………………………………….……23
3.2 OOK Receiver Architecture………………………………………………….…...24
3.2.1 Introduction…………………………………………………………….…...24
3.2.2 Description of Receivers……………………………………………...…….25
3.2.3 Block Diagrams of the OOK Receiver ……………………………..……26
3.2.3.1 Low voltage amplifier ….………………………………………….27
3.2.3.2 Cascaded gain amplifiers ……..…………………………………28
3.2.3.3 Demodulator circuit ……..………………………………………29
3.2.3.4 Comparator and buffer ..……………………………...……….……31
3.3 Simulation Result …………………………………………………….….……33
3.3.1 Gain Stages …….………………………………………….……………33
3.3.2 Demodulator Stage …..……………………………………………………34
3.3.3 Output Stage ………………………………………………..……………35
3.3.4 OOK Receiver with input matching …………………………………..39
3.4 Measurement Result …………………………………………………......………40
3.4.1 OOK Receiver without input matching ………………………....………..41
3.4.2 OOK Receiver with input matching ……………………...…………...49
3.5 Summary …….……………………………………………...…………………..54
Chapter 4 Received Signal Strength Indicator……………………...57
4.1 Introduction ………………………………..…………………………………57
4.2 Received Signal Strength …………………...…………………………...………58
4.2.1 Principle of RSSI ………...…………………………………...…………59
4.2.2 Architecture Design………..…..………………………………...…………62
4.2.2.1 Limiting amplifiers…………………………………….....…………62
4.2.2.2 Current rectifiers…………………………………….....……………63
4.2.2.3 OOK receiver with RSSI………………………….....…...…………66
4.3 Simulation ………………………………………………………………………..68
4.3.1 Simulation RSSI transfer curve……………………………...……………..69
4.4 Measurement Result …………………...………………………………………...70
4.5 Summary………………………………………………………….……………....75
Chapter 5 A Wireless RF Front-end Suitable for Channel Band
800MHz~1GHz…....………….………………………......79
5.1 Motivation ……………………………………………………...…...…………....79
5.2 System Architecture……………………………………………………………....81
5.2.1 Design of Low-Noise Amplifier…………………………………..………..83
5.2.1.1 Introduction …………..…………………………………..…..……83
5.2.1.2 Input matching of LNA ……………………………………………..83
5.2.1.3 Proposed low-noise amplifier……………………………………….88
5.2.2 Principle of Mixers …………………………………………..…..………..89
5.2.2.1 Gilbert mixer …………………………………..…………..………..89
5.2.2.2 Unbalanced active mixer ……..…………..…………..…………90
5.2.2.3 Single balanced active mixer …………..…………..………..…91
5.2.2.4 Modified Gilbert mixer ……………..…………..………………..…92
5.2.2.5 Proposed double balanced mixer …….………..………………..….93
5.2.3 Design of the IF Filter ……..……………….…...……………..………..96
5.2.4 Design of IF amplifiers …………….…………...………..……..………..96
5.3 Simulation of the RF Front-end Circuit …….……...………..……..…………..99
5.3.1 Simulation of the Low-noise Amplifier …….....………..……..………….99
5.3.2 Simulation of the Mixer ….........…..……..……………………………...101
5.4 Measurement Result ..…………..……..……………………………..................104
5.4.1 Conversion of the Output power ………..…………………..................105
5.4.2 Measurement of the Low-noise Amplifier ………..………..................105
5.4.3 Measurement of the Mixer .……..………………….............................107
5.4.4 IF Filter and the Demodulator......................................................................113
5.5 Summary and Discussion ……………………………………………………….116
Chapter 6 Conclusion…………………………………………..……121

[1.1] G. PULSE Co., Ltd, [online] http://www.gpulse.com/
[1.2] H. Yu, K. Najafi, “Low-Power Interface Circuits for Bio-Implantable Microsystems,“ ISSCC 2003 / SESSION 11 / MICROSENSORS AND BIOMEMS / PAPER 11.2
[2.1] Behzad Razavi, “RF Microelectronics,” Prentice Hall Inc.,1998.
[2.2] P. R. Gray and R. G Meyer, “Future Direction in Silicon ICs for RF Personal Communications,” in IEEE 1995 Custom Integrated Circuits Conference, 1995.
[2.3] B. Razavi, “Challenges in Portable RF Transceiver Design,” IEEE Circuits and Devices Magazine, vol. 12, pp. 12-25, Sept. 1996.
[2.4] C.C. Lin, ”CMOS RF Front-End Circuit Design for DECT system Application,” Master’s thesis, National Taiwan University, Taiwan, ROC, 2000
[2.5] J. Crols and M. S. J. Steyaert, “A Single Chip 900MHz CMOS Receiver Front End with a High Performance Low IF Topology,” IEEE Journal of Solid State Circuits, vol. 30, pp. 1483-1492, Dec. 1995.
[2.6] 林尹堯, “Design and Implementation of 1.9GHz CMOS Receiver RF front-end Circuits,” Master thesis, Graduate Institute of Electronics Engineering, National Taiwan University.
[2.7] 葉昆穎, “A Low Power Monolithic RF Receiver in HBT,” Master thesis, Graduate Institute of Electronics Engineering, National Taiwan University.
[3.1] K. Romer, F. Mattern, and E. Zurich, “The Design Space of Wireless Sensor Networks,” IEEE Wireless Communications, vol.11, no.6, pp.54-61, Dec. 2004.
[3.2] H. Yu and K. Najafi, “Low-Power Interface Circuits for Bio-Implantable Microsystems,” ISSCC Dig. of Tech. Papers, pp.194-487, Feb. 2003.
[3.3] D.H. Chae, K.H. Han, K.S. Lim, K.H. Seo, K.H. Won, W.D. Cho, and S.S. An, “Power Saving Mobility Protocol for Sensor Network,” IEEE Proc. Software Technologies for Future Embedded and Ubiquitous Systems, pp.122-126, May 2004.
[3.4] B.P. Otis, Y.H. Chee, R. Lu, N.M. Pletcher, and J.M. Rabaey, “An Ultra-Low Power MEMS-Based Two-Channel Transceiver for Wireless Sensor Networks,” Symp. VLSI Circuits, June 2004.
[3.5] V. Peiris, C. Arm, S. Bories, et al., “A 1V 433/868MHz 25kb/s-FSK 2kb/s-OOK RF Transceiver SoC in Standard Digital 0.18um CMOS,” ISSCC, pp.258-259, Feb. 2005.
[3.6] B. Otis, Y.H. Chee, and J. Rabaey, “A 400μW-RX, 1.6mW-TX Super-Regenerative Transceiver for Wireless Sensor Networks” ISSCC, pp.396-397, Feb. 2005.
[3.7] Y.T. Lin, T. Wang, S. S. Lu, and G. W. Huang, "A 0.5 V 3.1 mW Fully Monolithic OOK Receiver for Wireless Local Area Sensor Network," "IEEE International Asian Solid-State Circuit Conference, Hsin-Chu, Nov. 2005.
[3.8] Dennis Roddy, John Coolen, Electronic Communications, pp.272-276. Englewood Cliffs, NJ: Prentice-Hall, 1995.
[3.9] Electronics Communications, ISBN# [ 22A1982 ].
[3.10] Chi-Wei Tseng, “Wireless Bio-Medical Integrated Chip,” Master thesis, Graduate Institute of Electronics Engineering, National Taiwan University.
[4.1] S. Khorram, A. Rogougaran, and A. A. Abidi, “A CMOS Limiting Amplifier and Signal-Strength Indicator”, Symp. On VLSI Circuits, pp.95-96 1995.
[4.2] Po-Chiun Huang, Yi-Huei Chen, and Chorng-Kuang Wang, “A 2-V 10.7-MHz CMOS Limiting/Amplifier RSSI”, IEEE Journal of Solid State Circuits, vol.35, no.10, pp1474-1480, 2000.
[4.3] K. Kimura, ”A CMOS Logarithmic IF Amplifier with Unbalanced Source-Couple Pairs”, IEEE Journal of Solid State Circuits, vol.28, no.1, pp78-83, 1993.
[4.4] Analog Device. (1996) AD608 Low Power Mixer/Limiter/RSSI 3-V Receiver IF Subsystem. [Online] Available: http://www.analog.com
[4.5] R. S. Hughes, Logarithmic Amplification with Application to Radar and EW. Dedham, MA: Artech, 1986.
[4.6] Bluetooth specification v.1.0b, Part A Radio Specification pp.20-31 [Online]http://www.bluetooth.com, 1999
[4.7] CMOS Limiters with RSSIs for Bluetooth Receivers, Hong-Sun Kim, Mohammed Ismail, Fellow IEEE, and Hakan Olsson
[4.8] Z. Wang, “Full-wave precision rectification that is performed in current domain and very suitable for CMOS implementation,” IEEE Trans. Circuits Syst. I, vol. 39, pp. 456–462, June 1992.
[4.9] J. Ramirez-Angulo, “A precision broadband rectifier in CMOS technology,” in IEEE Int. Symp. Circuits and Systems, May 1990, pp. 1724–1727.
[4.10] M. S. Steyaert et al., “A CMOS rectifier-integrator for amplitude detection in hard disk servo loops,” IEEE J. Solid-State Circuits, vol. 30, pp. 743–751, July 1995.
[4.11] J. B. Kuo and J. H. Lou,‘Low-Voltage CMOS VLSI Circuits,’John Wiley, New York, ISBN 0471321052, Jan. 1999.
[5.1] [online] http://en.wikipedia.org/wiki/RFID
[5.2] IDTechEx, [online] http://www.idtechex.com/products/en/articles/00000528.asp
[5.3] D. J. Cassan and J. R. Long, “A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-um CMOS,” IEEE J. Solid- State Circuits, vol. 38, no. 3, pp. 427–435, Mar. 2003.
[5.4] T. P. Liu and E.Westerwick, “5-GHz CMOS radio transceiver front-end chipset,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1927–1933, Dec. 2000.
[5.5] J. Bouras, S. Bouras, T. Georgantas, N. Haralabidis, G. Kamoulakos, C. Kapnistis, S. Kavadias, Y. Kokolakis, P. Merakos, J. Rudell, S. Plevridis, I. Vassiliou, K. Vavelidis, and A. Yamanaka, “A digitally calibrated 5.15–5.825 GHz transceiver for 802.11a wireless LAN’s in 0.18 um CMOS,” in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2003, pp. 352–353.
[5.6] H. Samavati, H. R. Rategh, and T. H. Lee, “A 5-GHz CMOS wireless LAN receiver front end,” IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 765–772, May 2000.
[5.7] Andrea Bevilacqua and Ali M. Niknejad, “An Ultrawideband CMOS Low-Noise Amplifier for 3.1–10.6-GHz Wireless Receivers,” IEEE J. Solid-State Circuits, vol. 39, no. 12, DECEMBER 2004
[5.8] Tao Wang, Hsiao-Chin Chen, Hung-Wei Chiu, Yo-Sheng Lin, Guo Wei Huang, and Shey-Shi Lu, “Micromachined CMOS LNA and VCO By CMOS-Compatible ICP Deep Trench Technology,” IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 2, FEBRUARY 2006
[5.9] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,”
IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745–759, May 1997.
[5.10] R. Ludwig and P. Bretchko, RF Circuit Design—Theory and Applications. Upper Saddle River, NJ: Prentice-Hall, 2000, p. 607.
[5.11] S. S. Lu, Y. S. Lin, H. W. Chiu, Y. C. Chen, and C. C. Meng, “The Determination of S-Parameters From the Poles of Voltage-Gain Transfer Function for RF IC Design,” IEEE Trans. on Circuits and Systems - I, vol. 52, no. 1, pp. 191-199, Jan. 2005.
[5.12] Hung-Ta Chou, “A Frequency-Shift-Keying Transceiver for Bio-Medical Signals,” Master thesis, Graduate Institute of Electronics Engineering, National Taiwan University.