臺灣博碩士論文加值系統

隨著電路技術進步，先進製程有越來越適合數位電路設計的優點。為了要跟上市場需求，小晶片面積與低電源供應器電壓已成為現今的一種趨勢。而在更換製程時，數位電路也有容易重新設計的特性。
全數位式鎖相迴路可以將類比的電荷幫浦與迴路濾波器以數位式的電路來取代，是對於積體電路來說的一大好處。
時脈展頻產生器應用於許多系統中，時脈展頻產生器可以將處生的時脈經由展頻功能，將主要的頻率能量分散，降低其每單位頻寬的輻射功率。
本論文為應用於時脈展頻器之全數位式鎖相迴路。在此使用了兩段式的三角積分調變器去增加使用於展頻功能上調變器的解析度。最後，此晶片是提請台積電的90奈米製程製作。

Recent advances in integrated circuit (IC) technology make fabrication processes very suitable for digital design. In order to satisfy the market requirement, small area and low voltage designs are mandated nowadays. It is easy to redesign with process changes for digital designs.
The all-digital phase-locked loop (ADPLL), one of the most recent and significant advancements in the integrated circuits, offers the remarkable advantage of replacing the charge pump and the loop filter with digital loop filter.
The spread spectrum clock generator (SSCG) can be applied to many systems due to its characteristic of spreading the energy of frequency harmonics and reducing the radiated power per unit bandwidth.
In this thesis, an all-digital phase-locked loop application for SSCG is implemented in this paper. We use two-stage delta-sigma modulator to improve the resolution of DSM in spread-spectrum clock function. Finally, the experimental ship is fabricated in a TSMC 90nm CMOS process.

誌謝 i
摘要 iii
Abstract iv
Contents v
List of Figures ix
List of Tables xi
Chapter 1 1
1.1 Introduction 1
1.2 Thesis Organization 2
Chapter 2 5
2.1 Introduction 5
2.2 Spread Spectrum Fundamentals 6
2.2.1 Modulation profiles 6
2.2.2 Spread Spectrum Modes 8
2.2.3 Spread Spectrum Methods [7] 10
Chapter 3 13
3.1 Basic Concept 13
3.2 Model of an APLL [9] 16
3.2.1 Linear Model for a P2D 16
3.2.2 Linear Model for a DLF 18
3.2.3 Linear Model for a DCO and divider 22
3.3 Determine the parameters of an APLL 23
3.3.1 Design Parameters Calculation for 1st Order DLF 24
3.3.2 Design Parameters Calculation for 2st Order DLF 27
3.3.3 Noise Transfer Function [14] 29
Chapter 4 33
4.1 Introduction 33
4.2 System and Circuit Implement for ADPLL 34
4.2.1 Overview for ADPLL 34
4.2.2 Phase / Frequency Detector and Time to Digital Converter 35
4.2.3 Digital Loop Filter 41
4.2.4 Digital-Controlled Oscillator [21] 44
4.2.5 Programmable Divider 51
4.2.6 TSPC Divider 52
4.3 System and Circuit Implement for SSCG 53
4.3.1 Two-Stage Delta-Sigma Modulation for SSCG 54
4.3.2 Calibration of the Varactor 56
4.3.3 Compensation of Two-Stage DSM 59
4.4 System Simulation 62
4.4.1 Simulate and Verify System 62
4.5 Summary 68
Chapter 5 71
5.1 Introduction 71
5.2 Layout and Floor plan 71
5.3 Test Strategy 73
5.3.1 Test Setup 73
5.3.2 FPGA Setup 74
5.3.3 Print Circuit Board Design 74
5.4 Chip Die Photo 75
5.5 Experimental Results 76
Chapter 6 81
Bibliography 83
Biography 88

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