臺灣博碩士論文加值系統

H.264 視訊壓縮標準在移動估測部分採用可變區塊比對演算法，這需要付出大量的計算時間與資料處理，佔用視訊壓縮大部分的時間。然而在移動估測中，區塊比對演算法有相當高的資料相關性以及規則性，很適合用於大量平行處理的硬體電路來完成。在過去多年來的文獻中，文獻[23]提出的硬體架構可以有效處理所有不同大小的區塊，並有較低的計算延遲和高度的計算吞吐量。本論文以此VLSI架構為基礎，設計可調式VLSI架構於H.264移動估測電路，將處理候選區塊的處理單元模組化，讓使用者在追求高效能與低成本的考量下，選擇合適數量的處理單元，大幅提升延展性。另一方面，本論文提出在局部記憶體只使用四個暫存器進行移動估測，改善硬體架構在局部記憶體使用較多暫存器的缺點。

中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章 緒論 1
1.1 研究背景與研究動機 1
1.2 全文架構 3
第二章 基本原理介紹 4
2.1 H.264視訊壓縮標準 4
2.2 移動估測與移動補償 5
2.3 區塊比對演算法 7
2.3.1 全域搜尋區塊比對演算法 8
2.4 絕對誤差總和 9
2.5 H.264可變區塊比對演算法 10
2.6 心脈陣列架構 11
2.6.1 心脈陣列處理器 11
2.6.2 一維心脈陣列 12
2.6.3 串接一維心脈陣列 14
第三章 可調式VLSI架構於H.264移動估測電路 17
3.1 移動估測單元 17
3.2 處理單元(Processor Unit, PU)設計 18
3.2.1 H.264可變區塊比對演算法分析 19
3.2.2 絕對誤差總和模組 21
3.2.3 可變區塊移動估測處理器 27
3.3 移動向量選擇模組 27
3.4 控制單元設計 28
第四章 實驗結果與效能分析 29
4.1 實驗環境與步驟 29
4.2 實驗結果 35
4.3 效能分析 39
第五章 結論與未來展望 42
參考文獻 43

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