臺灣博碩士論文加值系統

在此篇論文的研究中，我們是第一個提出用非等向性的乾式蝕刻的方式形成溝槽式超薄主動層(2.4nm)N型鰭式閘極無接面式多晶矽薄膜電晶體(trench JL-FET)的研究。在此研究中我們利用乾式蝕刻方式將主動層薄化去取代直接沉積一層薄膜主動層的傳統方式，此方式相較於直接沉積薄主動層可以得到較大的晶粒與較少的晶界，以使元件展現極佳的電性。此溝槽式主動層結構能同時定義出元件的通道厚度及有效閘極長度，且非常相容於無接面式電晶體的製程。此元件擁有優越的SS值100mV dec-1 以及極佳的開關特性(ION/IOFF > 107)。另外，此元件在抑制短通道效應上也展現出極佳的能力，其實測的DIBL值近似為0mV/V，主要是因為主動層通道薄化到2.4nm的因素。我們有做不同元件尺寸的展現，以證明這種乾式蝕刻的方式非常穩定，製程簡單並且可以應用到現今及未來的製程科技上面。
在此篇研究中，我們首先專注於元件製程細節以及典型的電晶體元件特性分析。在元件分析上我們用一個擁有溝槽式超薄主動層(2.4nm)無接面式電晶體元件(trench JL-FET)與一個傳統主動層(25nm)無接面式電晶體(conventional JL-FET)元件做比較，值得一提的是此溝槽式超薄主動層元件的輸出電流值比傳統主動層元件的輸出電流值高約2.5倍，主要是因為通道夠薄，使之產生的量子侷限效應提升電子遷移率(mobility)，我們同時也用3D元件模擬去得到相同的效果。
接著我們對此元件做了多種可靠度分析的研究。第一種可靠度分析是在此元件對高溫環境的電性劣化反應，第二種可靠度分析是在此元件對高壓條件下的崩潰反應。
在高溫可靠度分析討論中，我們同時做了傳統無接面式電晶體(conventional JL-FET)與溝槽式無接面式電晶體(trench JL-FET)來比較，可以看到此溝槽式超薄主動層元件的VTH與SS隨著溫度增高所劣化的程度非常小，這主要是因為主動層薄化的程度使元件呈現在近似完全空乏的狀態以及多晶矽薄膜通道接近單晶的現象。另外，此溝槽式超博主動層元件隨著溫度升高仍能保有較低的漏電特性，主因是量子侷限效應所導致。
在高壓崩潰機制的可靠度分析上，我們將此溝槽式無接面電晶體(trench JL-FET)與我們實驗室之前做的傳統反轉式接面電晶體(IM-FET)做比較，並同時展現電流開通狀態與關閉狀態的崩潰現象。此研究搭配3D結構的TCAD元件模擬去看其電場在元件中的分布，實際量出電流關閉狀態的溝槽式無接面電晶體(trench JL-FET)的崩潰電壓為73V遠大於傳統街面式電晶體(IM-FET)，主要是因為無接面電晶體沒有PN接面，通道中的電場最大值較小而降低了碰撞電離率(impact ionization rate)。
溝槽式超薄主動層N型鰭式閘極無接面式多晶矽薄膜電晶體具有非常大的潛力去應用在未來3D堆疊結構、高功率輸出元件、低消耗功率元件以及高壓電晶體元件。

In this study, we describe the fabrication of a trench junctionless poly-Si field-effect transistor (trench JL-FET) with 2.4 nm ultra-thin channels. The dry etching process is utilized firstly in the fabrication of trench JL-FET is used to form a trench and define the channel thickness (TCH) and the gate length (LG) simultaneously. The trench structure was successfully and easily integrated into the JL-FET device. This work use the dry etching to form the ultra-thin channel instead of directly depositing the thin-film as the poly-Si channel in JL FETs and it could get larger grain size and less grain boundary than directly depositing the thin-film. The trench JL-FET has superior SS value about 100 mV dec-1, high ION/IOFF ratio up to 107 and practically negligible DIBL value. To confirm the stable process of trench and potential of advanced CMOS process, we have shown the trench JL-FET with different channel width and gate length.
In this study of characteristics analysis, we firstly focus on detail fabricating process and typical electrical characteristics. It’s compare the trench JL-FETs (TCH=2.4nm) with the conventional JL-FETs (TCH=2.4nm). It’s worth to be mentioned that the saturation currents of trench JL-FETs are higher than that of conventional JL-FETs, owing to quantum confinement effect (QCE) in ultra-thin channel. The quantum confinement effect can improve the carrier mobility and electron velocity which is confirmed by TCAD simulation.
Next, this work had shown the reliability analysis including high temperature performance and high voltage breakdown mechanism.
This study investigated the temperature dependence on ID-VG curves of trench JL-FETs and conventional JL-FETs. The VTH and SS of trench JL-FETs are less sensitive to temperature than that of conventional JL-FETs that maybe due to the single crystal-like channel and fully-depleted state in the ultra-thin channel. Additionally, The trench JL-FET devices exhibit extremely small leakage currents as increasing temperature due to the energy subbands of quantum confinement effect.
Finally, the breakdown mechanisms of JL-FETs and inversion mode (IM) FETs with different gate bias condition (on-state and off-state) are discussed completely and confirmed by experimental and simulated results. The simulated results show the maximum electric field of JL-FET is smaller than IM-FET, so the measured breakdown voltage (VBD) of JL device is 73V which is better than that of IM device.
the trench JL-FET has a great potential for using in advanced AMLCD, 3D stacked applications, low power consumption applications , system-on-panel and high voltage power MOS devices.

中 文 摘 要 i
Abstract iii
Acknowledge v
Contents vi
Table Captions vii
Figure Captions viii
Chapter 1 1
Introduction 1
1-1 Introduction of Junctionless Device 1
1-2 Motivation 6
1-3 Thesis Organization 12
Chapter 2 13
Junctionless Mechanism 13
2-1 Basic Principle of Junctionless Transistor 13
2-2 Short Channel Effect (SCE) in Junctionless Transistor 17
2-3 Quantum Confinement Effect (QCE) in Ultra-Thin Body 19
Chapter 3 23
Device Fabrication and Device Simulation 23
3-1 Device Fabrication Process 23
3-2 Device Simulation 25
Chapter 4 27
Characteristics Analysis 27
4-1 The TEM, SEM and atomic force microscopy (AFM) images 27
4-2 Device Characteristics Analysis 29
4-3 Quantum Confinement Effect Discussion with Experiment and Simulation Results 33
4-4 Device Temperature Performance 37
4-5 Breakdown Discussion 40
4-6 Conclusion 44
Chapter 5 45
Conclusion 45
Reference 47

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