臺灣博碩士論文加值系統

本論文討論分為兩部份，第一部份探討適用於 TSMC 0.18-µm CMOS製程壓控振盪器，利用電流再利用的電路架構，我們可以動態地節省直流功率消耗，在1.2 V的供給電壓下，達到0.9 mW的功率消耗(不包括緩衝級)。測量結果得知在操作頻率5.4 GHz 左右有140 MHz 的可調範圍。為了達到高輸出功率，我們使用疊接架構的緩衝級來增加輸出功率，因而達到輸出功率為 -2.06 dBm；相位雜訊方面為 -112.7 dBc/Hz @ 1 MHz，經由計算可得FOM (Figure of merit) 約為 -188 dBc/Hz。
第二部份則提出一種使用微帶線 (Micro-strip line) 的方式來取代 TSMC 螺旋電感 (Spiral inductor)，其一可節省晶片佔用面積，其二微帶線的低損耗特性可以使訊號源不易輻射。此外，使用反轉模式 (Inversion-mode) 的可變電容。這類型電容的品質因素比傳統MOS可變電容高，可得到較寬頻的可調範圍及較好的相位雜訊。雙推式的振盪器，有易做到高頻段振盪，及高效能等等的優點，為目前常見做到高頻振盪的方式之一。利用ADS模擬，操作頻率在50 GHz，有0.88 GHz的可調範圍，且相位雜訊為 -100 dBc/Hz @ 1 MHz，經由計算可得FOM 約為-180 dBc/Hz。

CHAPTER 1 INTRODUCTION 1
1.1 BACKGROUND AND MOTIVATION 1
1.2 THESIS ORGANIZATION 4
CHAPTER2 PHASE NOISE IN VCO 5
2.1 INTRODUCTION 5
2.2 PHASE NOISE 6
2.2.1 Basic Concept of Phase Noise 6
2.2.2 Phase Noise in OFDM Signal 7
2.3 LINEARITY AND TIME-INVARIANT MODEL OF VCO 8
2.4 LINEARITY AND TIME-VARIANT MODEL OF VCO 10
2.5 DEFINITION OF PHASE NOISE 11
CHAPTER3 CURRENT-REUSED VCO 12
3.1 INTRODUCTION 12
3.2 CONVENTION CROSS-COUPLED VCO VERSUS CURRENT-REUSED VCO 13
3.3 CURRENT-REUSED VCO CIRCUIT DESIGN 15
3.3.1 Architecture Description 15
3.3.2 Phase Noise versus Tuning Range 18
3.4 CHIP LAYOUT AND SIMULATION RESULTS 21
3.5 MEASUREMENT RESULTS AND DISCUSSION 24
3.5.1 Measurement Consideration 24
3.5.2 Measurement Result 25
3.6 SIMILAR CIRCUIT COMPARISON 29
3.6.1 Circuit Schematic 29
3.6.2 Chip Layout and Simulation Results 30
CHAPTER4 PUSH-PUSH 50 GHZ VCO 35
4.1 INTRODUCTION 35
4.2 50GHZ PUSH-PUSH VCO CIRCUIT DESIGN 37
4.2.1 Architecture Description 37
4.2.2 Inversion-Mode Varactor 38
4.2.3 Thin-Film Micro-Strip Line 40
4.3 CHIP LAYOUT AND SIMULATION RESULTS 42
4.4 DISCUSSION 48
REFERENCES 50

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