臺灣博碩士論文加值系統

本論文以TSMC 0.18μm 1P6M CMOS製程研製2.4GHz ISM頻帶CMOS功率放大器。第一部分是探討功率放大器的設計，輸出級的輸出匹配網路中的電感則採用雙層金屬纏繞的方式，提升電感的Q值，減少損耗，以提高功率附加效率。量測結果顯示功率放大器在2.4GHz其增益有19dB，在P1dB壓縮點的輸出功率與PAE為20dBm與25%，最大輸出功率與PAE分別為22.5dBm與36%。

第二部分則是提升效率的方法，相較於傳統的功率放大器架構，本論文提出電流再利用(Current reused)的技巧，讓兩級的功率放大器使用相同的電流，以減少直流功率的消耗，進而去提高功率附加效率。模擬結果顯示功率放大器在2.4GHz其增益有18.8dB，在P1dB壓縮點的輸出功率與PAE為19.3dBm與31%，最大輸出功率與PAE分別為19.9dBm與36%。

This thesis presents the development of 2.4GHz ISM-band CMOS power amplifier in TSMC 0.18um 1P6M CMOS process. The first main part is on the design of power amplifier. We use two layer metal lines to design the inductor in output matching network at output stage. It can increase the Q factor, and reduce the loss, the PAE can be improved. The measurements have shown this power amplifier provides a gain of 19dB at 2.4GHz, and the output power transmits 20dBm power with 25% power added efficiency at 1-dB compression point. The maximum output power of this amplifier is 22.5dBm with its power added efficiency as 36%.

The second main part is a method of improving the efficiency. Compared with the conventional architectures of power amplifier. We presented the circuit technique of current reused. To make the two stage power amplifier using the same current, and improving the power added efficiency by reducing the DC power consumption. The simulations have shown this power amplifier provides a gain of 19dB at 2.4GHz, and the output power transmits 18.8dBm power with 31% power added efficiency at 1-dB compression point. The maximum output power of this amplifier is 19.9dBm with its power added efficiency as 36%.

摘要 I
ABSTRACT II
目錄 III
圖目錄 VI
表目錄 XI
第一章 1
緒論 1
1.1 無線通訊發展現況 1
1.2 研究動機 3
1.3 章節規劃 4
第二章 5
射頻功率放大器基本理論 5
2.1 功率放大器規格介紹 5
2.1.1 S參數 5
2.1.2 穩定度 6
2.1.3 功率增益 8
2.1.4 P1dB壓縮點 9
2.1.5 效率 10
2.2 功率放大器的分類 11
2.2.1 A類 功率放大器 11
2.2.3 AB, B and C 類功率放大器 12
2.2.3 D類 功率放大器 16
2.2.4 E類 功率放大器 17
2.2.4 F類 功率放大器 18
2.3 線性度 20
2.3.1 AM-AM/AM-PM 轉換特性 20
2.3.2 鄰近通道功率比 (ACPR) 22
2.3.3 頻譜遮罩 (Spectral Mask) 23
2.3.4 錯誤向量強度(Error Vector Magnitude, EVM) 23
2.4 功率匹配技巧 25
2.4.1 負載線原理 25
2.4.2 模擬軟體量測 30
2.4.3 負載拉移量測系統(Load-Pull Measurement System) 31
第三章 33
功率放大器設計與量測結果 33
3.1 CMOS功率放大器設計 33
3.2 架構簡介 33
3.3 設計方法與流程 36
3.4 模擬結果 42
3.5 Layout 佈局說明 46
3.6量測分析 47
第四章 53
利用Current reused技巧之CMOS功率放大器設計與量測結果 53
4.1 架構簡介 53
4.2 設計方法與流程 56
4.3 模擬結果 62
4.4 Layout 佈局說明 68
4.5 量測分析 69
4.6 問題與討論 72
第五章 83
總結 83
5.1 結論 83
5.2 未來展望 84
參考文獻 85

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