臺灣博碩士論文加值系統

本論文研製應用於IEEE 802.15標準之超寬頻通訊及毫米波通訊之帶通濾波器。超寬頻(3.1-10.6 GHz)帶通濾波器是以多模態共振器為基礎，在通帶內產生三個諧振模態，並設計輸入和輸出寬頻阻抗轉換網路，達到寬頻阻抗匹配，和產生通帶外之傳輸零點，以增加禁帶拒斥值。電路以RO4003基板實現，電路尺寸為2.79×1.35 cm2。量測結果顯示3.1-10.6 GHz通帶內之植入損耗為1.4 dB，返回損耗為17.0 dB，群速延遲時間小於0.8 ns，傳輸零點分別位在2.2 GHz及11.8 GHz，造成通帶邊緣有40-70 dB/GHz的滾降率(roll-off)，頻率外拒斥值在2 GHz以下為35 dB，在12-14.5 GHz為25 dB。
毫米波帶通濾波晶片，共有三個電路，分別使用TSMC 0.18-um、0.13-um CMOS製程實現。晶片濾波器的設計，除了植入損耗、頻帶選擇性外，晶片面積必須足夠小。因此在本論文中以彎折式步階阻抗共振器，再加上地面浮升技術，可讓晶片面積小於0.05 。第一個晶片濾波器為CMOS 0.18-um 60GHz帶通濾波器，量測結果在58-66.7 GHz通帶內，植入損耗為3.0-3.5 dB，返回損耗小於23.7 dB，傳輸零點分別位在45.4 GHz及82.0 GHz，不包含接觸片面積為0.224 mm2。第二個晶片濾波器為CMOS 0.18-um 60GHz帶通濾波器，量測結果在55.2-63.6 GHz通帶內，植入損耗為3.5-3.7 dB，返回損耗小於10.2 dB，傳輸零點分別位在36.4 GHz及81.0 GHz，不包含接觸片面積為0.074 mm2。第三個晶片濾波器為CMOS 0.13-um 77GHz帶通濾波器，量測結果在74.8-83.7 GHz通帶內，植入損耗為3.9-4.5 dB，返回損耗小於12.5 dB，傳輸零點分別位在60.9 GHz及109.2 GHz，不包含接觸片面積為0.08 mm2。量測結果與模擬結果符合，驗證本論文提出之地面浮升技術，確實可以大幅縮小晶片面積，達到毫米單晶片系統的需求。

This thesis investigates compact and high-performance bandpass filters for IEEE 802.11.15 ultra-wideband and millimeter-wave applications. The ultra-wideband (3.1-10.6 GHz) bandpass filter was designed based on the multiple-mode resonant technique, where three resonant modes are generated in the passband to attain wide passband. Meanwhile, a novel input/output impedance transformation networks was designed for both wideband impedance matching in passband and transmission-zero generation in stopband. The filter circuit was realized on RO4003C substrate, where the circuit size is 2.79 × 1.35 cm2. The measurement results show that the insertion loss is less than 1.4 dB, the return loss is greater than 17 dB and group delay is less than 0.8 ns in 3.1-10.6 GHz passband. The two transmission zeros located at 2.2 GHz and 11.8 GHz, respectively, such that a sharp roll-off-rate 40-70 dB/GHz is obtained and a good stopband rejection of better than 35 dB below 2 GHz and 25 dB in 12-14.5 GHz is achieved.
On the other hand, three millimeter-wave bandpass filter were designed in 0.18-um 1P6M and 0.13-um 1P8M standard CMOS technology. We presented a compact stepped-impedance resonator with a raised-ground plane to achieve an extraordinary compact chip filter with size less than 0.05 . The first chip is a 60 GHz CMOS 0.18-um bandpass filter, where the measured insertion loss is 3.0-3.5 dB and the return loss is larger than 23.7 dB in 58-66.7 GHz. Two transmission zeros are generated at 45.4 and 82.0 GHz. The chip size without input and output GSG pad is 0.224 mm2. The second chip achieved a measured insertion loss of 3.5-3.7 dB, the return loss of 10.2 dB in 55.2-63.6 GHz and two transmission zeros at 36.4 and 81.0 GHz. The chip size without pad is 0.074 mm2. The third chip has measured insertion loss of 3.9-4.5 dB, the return loss of less than 12.5 dB in 74.8-83.7 GHz and two transmission zeros at 60.9 and 109.2 GHz. The chip size without pad is 0.08 mm2. The measurement results agree very well with EM simulation. This demonstrates the proposed raised-ground plane technique can efficiently reduce the filter chip size while keeping high filter performance.

目錄 i
圖目錄 iiii
表目錄 vii
第一章 緒論
1.1 超寬頻與毫米波通訊技術之發展與簡介
1.2 研究背景與動機
1.3 文獻探討
1.3.1 超寬頻帶通濾波器
1.3.2 毫米波CMOS帶通濾波器
第二章 超寬頻帶通濾波器之分析與設計
2.1 多模態共振器超寬頻濾波器之文獻回顧
2.2 多模態超寬頻濾波器
2.2.1 倒T型多模態共振器分析
2.2.2 倒F型阻抗轉換網路
2.3 電路設計
2.4 模擬與量測結果
第三章 運用接地浮升技術之毫米波CMOS帶通濾波器設計與分析
3.1 電路架構介紹
3.1.1 步階阻抗共振器之共振模態
3.1.2 傳輸零點之控制
3.2 接地浮升技術之分析
3.3 電路設計
3.4 模擬與量測結果
3.4.1 CMOS濾波器A型
3.4.2 CMOS濾波器B型
3.4.3 CMOS濾波器C型
3.5 CMOS濾波器特性比較
第四章 結論
參考文獻

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