臺灣博碩士論文加值系統

通訊系統在這幾年來不斷地在進化，愈來愈快速的資料在進行傳輸與接收，而其相對應的驗證系統也扮演著舉足輕重的地位。
　　本論文提出一個利用40奈米互補式金屬氧化半導體製程製作之高速偽隨機二進位序列產生器(PRBS Generator)，其功能為發送出4種不同樣式的資料序列：2^7 – 1、2^15 – 1、2^23 – 1、2^31 – 1，而資料的速率則是由外部灌入的時脈來決定，可以達到40 Gb/s。
　　序列產生器的電路架構與有線背板通訊系統的發送器相似，由多工器、正反器、除頻器、前饋等化器所組成，而由於傳統的頻率合成器其操作頻率範圍有限，所以這邊的序列產生器採用了外部灌入的時脈，由半速率的時脈來觸發全速率的資料序列作為輸出，再利用前饋等化器作為輸出級，來補償資料在通道的傳送所造成的損失。在量測上，由於儀器所能提供的時脈最高只到20 Gb/s，所以最高量到40 Gb/s的資料序列輸出，雙端差動的擺福達到800 mV，功率消耗為600 mW, 我們可以利用外部的可程式化開發版來選擇序列的樣式，此外，輸出的4種序列在位元錯誤偵測器能操作的頻率範圍下(5 Gb/s ~ 32 Gb/s)進行比對驗證，皆為真。

口試委員會審定書 #
中文摘要 i
ABSTRACT ii
CONTENTS iii
LIST OF FIGURES v
LIST OF TABLES viii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization of the Thesis 3
Chapter 2 Introduction of Pseudo Random Binary Sequence 4
2.1 The Principle of Pseudo Random Binary Sequence 4
2.2 The Method of Realizing Pseudo Random Binary Sequence 5
Chapter 3 A High-Speed Pseudo Random Binary Sequence Generator 9
3.1 Architecture 9
3.2 The Digital Part 10
3.2.1 Structure 10
3.2.2 64:16 MUX 11
3.2.3 16:4 MUX 14
3.2.4 4:2 MUX 19
3.2.5 Timing Issue 20
3.3 The Final 2:1 MUX with Half-Rate Feedforward Equalizer 22
3.3.1 Feedforward Equalizer 22
3.3.2 Structure 24
3.3.3 Latch and Selector 26
3.3.4 Output Driver and Pre-Driver 29
3.3.5 Clock Input Driver 32
3.4 Phase Alignment Circuit 32
3.4.1 Timing Issue in the Final 2:1 MUX 32
3.4.2 Structure 33
3.4.3 Bang-Bang Phase Detector 34
3.4.4 Phase Interpolator & Up/Down Counter 35
3.4.5 Loop Behavior 36
3.4.6 Other Issue 38
3.5 Off-Chip Levels 40
3.5.1 Introduction 40
3.5.2 Bond Wire 42
Chapter 4 Measurement Results 45
4.1 Setup 45
4.2 System Integration 47
4.3 Module Measurement Results 49
4.4 Future Works 52
Chapter 5 Conclusions 55
Bibliography 56

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