臺灣博碩士論文加值系統

為了追求元件更快之操作速度以及降低製程成本，電晶體的通道長度也隨著時代演進而不段的進行微縮，為了抑制無可避免且越趨嚴重的短通道效應，諸多先進製程被運用在元件製程技術上，如應力矽技術、多閘極結構以及口袋佈植等技術，但仍被無法抑制之漏電流以及次臨界擺幅無法低於60mV/dec之問題所困擾。利用能帶間穿隧來當作傳導機制的穿隧式電晶體被提出，穿隧式場效電晶體利用與傳統反轉式截然不同之機制，可達到低於60mV/dec之次臨界擺幅以及利用接面間的高能障來抑制漏電流，亦可以在通道微縮時擁有較好之短通道效應免疫力，成為了下一個世代低功率元件之熱門候選人之一。
本論文對具多晶矽通道之穿隧式電晶體進行研究，多晶矽通道內之晶粒邊界上含有大量缺陷，缺陷中帶有大量懸浮鍵以及應力鍵，使得元件在操作時特性受到劣化，其中包括漏電流上升、開啟電流不夠大和次臨界擺幅不夠陡峭等等，本論文提出以氨氣電漿處理來鈍化晶粒邊界內的陷阱電荷，藉由降低晶粒邊界陷阱能態以及界面陷阱能態來提升元件性能。經實際量測後經表面電漿處理之元件在室溫情況下無論是在開啟電流、最小電流、次臨界擺幅和臨界電壓的都能比未經表面電漿處理之元件展現更好之特性，在通道微縮的情況下也依然擁有極佳之短通道效應免疫力。在可靠度方面，經表面電漿處理後之元件在經正偏壓應力1000秒後仍展現比對照組更好之可靠度。經氨氣表面電漿處理使得多晶矽穿隧式場效電晶體在各方面展現出更出色的特性並使其在電子產品上的運用更加廣泛以及達到更高的效能。

To obtain the faster operation speed and lower cost in fabrication，Channel length is continuously scaling down. However, negligible short channel effect(SCE) are observed and lead to increased of leakage current and reduce gate control ability. Tunnel Field-effect transistor is proposed to replace MOSFET in future. Unlike traditional inversion mode transistors, band-to-band tunneling is the mainly carrier transport mechanism. The subthreshold swing(S.S.) of T-FET can overcome the limitation of 60mV/dec of MOSFET.T-FET can also suppressed the leakage current by the high energy barrier and perform a better SCE immunity. T-FET is considered a promising candidate for next generation low power applications.
This thesis is mainly study for T-FET with Polycrystalline-Si channel, the channel film and the surface oxide interface of channel are rich with defects, lots of dangling bonds and strain bonds are localize in the defect. Both of them would degrade S.S. and increase leakage current. In this thesis,NH3 plasma is used to passivate the trap state. Both grain boundary trap state and interface trap can be effectively reduce by NH3 surface plasma treatment. Significant performance improvement has been observed after NH3 plasma surface treatment. Moreover, T-FET which passivated by NH3 plasma show lower
degradation after positive bias stress for 1000 sec, it indicate that TFET can perform higher reliability by NH3 plasma surface treatment. As a result, Poly-Si T-FET with NH3 plasma surface treatment can obtain better propertied and suitable to be used in LCD, three Dimensional-integrated Circuit or other consumer electronic.

論文審定書 i
致謝 ii
摘要 iv
Abstract v
目 錄 vi
圖目錄 ix
表目錄 xii
第一章 緒論 1
1.1前言: 1
1.2薄膜電晶體(Thin-film Transistors，TFT) 2
1.3短通道效應(Short Channel Effect) 2
1.3.1汲極引致能障降低(Drain-induced Barrier Lowering，DIBL) 3
1.3.2穿透崩潰(Punch Through) 3
1.4多晶矽和非晶矽 3
1.4.1晶粒邊界(Grain Boundary) 4
1.4.2表面電漿處理(Surface Plasma Treatment) 5
1.5多晶矽薄膜電晶體之可靠度機制 5
1.5.1正偏壓應力(Positive Bias Stress，PBS) 5
1.5.2負偏壓應力(Negative Bias Stress，NBS) 6
1.5.3熱載子效應(Hot Carrier Effect) 6
1.6穿隧式場效電晶體(Tunnel Field-effect Transistor，T-FET) 6
1.6.1穿隧式場效電晶體載子傳輸機制 7
1.6.2 Shockly-Read-Hall產生與復合 7
1.6.3陷阱輔助穿隧(Trap-assisted Tunneling) 8
1.6.4能帶至能帶穿隧(Band-to-band Tunneling，BTBT) 8
1.6.5多晶矽穿隧式場效電晶體 9
1.7研究動機 10
第二章 實驗步驟與流程 19
2.1元件製作 19
2.2電性參數萃取 20
2.2.1臨界電壓(Threshold Voltage) 20
2.2.2次臨界擺幅(Subthreshold Swing) 20
2.2.3開啟電流和最小電流(On-state Current & Minimum Current) 21
2.2.4晶粒邊界陷阱能態(Grain Boundary Trap State) 21
2.2.5界面陷阱能態(Interface Trap State) 22
第三章 結果與討論 30
3-1常態量測 30
3-2可靠度分析 32
第四章 總結與未來展望 43
參考文獻 44

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