臺灣博碩士論文加值系統

在這篇論文中，我們利用反應式射頻濺鍍銩氧化物、銩鈦氧化物、鎰鈦氧化物和鈥鈦氧化物將其應用在金屬-氧化物-半導體閘極介電層之電性及物性研究。首先藉由在銩閘極氧化物、鎰閘極氧化物和鈥閘極氧化物中混合鈦金屬，並使用O2快速退火來進行融合，更進一步探討結晶溫度、漏電流、介電常數和介面缺陷密度等特性。銩鈦閘極氧化物、鎰鈦閘極氧化物和鈥鈦閘極氧化物相較於銩閘極氧化物、鎰閘極氧化物和鈥閘極氧化物有較佳的電性如較高的電容值、較低漏電流密度與較薄的介面層，這可歸因於鈦金屬與銩閘極氧化物和鈥閘極氧化物相互融合所造成的因素。我們也發現到當退火溫到達到800℃時，銩鈦閘極氧化物、鎰鈦氧化物和鈥鈦閘極氧化物相較於其他退火溫度下有較高電容值並且有較少的遲滯現象和介面缺陷密度，也幾乎可以忽略在高常數電壓應力下的電荷缺陷現象。這些現象我們憑藉X-ray diffraction和X-ray photoelectron spectroscopy分析，可以歸因於非結晶性的銩鈦閘極氧化物、鎰鈦氧化物和鈥鈦閘極氧化物結構和降低介面層與銩矽酸鹽、鎰矽酸鹽和鈥矽酸鹽的生成。在文中也展示出藉由快速退火製程形成的銩鈦閘極氧化物、鎰鈦氧化物和鈥鈦閘極氧化物有相當高的介電常數來達成超薄的等效厚度，其中也包含較低的遲滯現象、介面缺陷密度、漏電流密度和良好的可靠度，是由於非結晶性的微結構和較薄的低介電介面層所造成的影響。

In this thesis, we reported on structural and electrical characteristic of high-k thulium oxide (Tm2O3), tulium titanium oxide (Tm2Ti2O7), ytterbium titanium oxide (Yb2TiO5) and holmium titanium oxide (HoTiO5) the metal-oxide-semiconductor capacitance gate dielectrics by reactive RF sputtering. Effect of titanium content in thulium oxide, ytterbium oxide and holmium oxide of the gate dielectrics with post deposition O2 annealing treatment on the crystallization temperature, leakage current, dielectric constant, and interface trap density. Compared to Tm2O3, Tm2Ti2O7, Yb2TiO5, and HoTiO3 was found to exhibit excellent electrical property such as a high accumulation capacitance, low leakage current density and a thin interfacial layer. The superiority of Tm2Ti2O7, Yb2TiO5, and HoTiO3 can be attributed to the addition of titanium the thulium oxide and holmium oxide matrix. It is found that the capacitance value of Tm2Ti2O7, Yb2TiO5, and HoTiO3 gate dielectric annealed at 800°C is higher compared to the other annealing temperatures and exhibits a lower hysteresis voltage as well as interface trap density in C-V curves. They also show almost negligible charge trapping under high constant voltage stress. This phenomenon is attributed to an amorphous Tm2Ti2O7, Yb2TiO5, and HoTiO3 structure and the decrease of the interfacial layer and Tm and Ho silicate thickness observed by X-ray diffraction and X-ray photoelectron spectroscopy, respectively. In addition, we reported Tm2Ti2O7, Yb2TiO5, and HoTiO3 compound layers grown by PDA process should display a sufficiently high-k value to achieve very thin EOT values, combined with lower hysteresis voltage, interface trap density, low leakage current density, and good reliability. This is due to the formation of amorphous microstructure and the reduction of lower-k interfacial layer.

Contents
誌謝 i
摘要 iii
ABSTRACT v
Contents vii
Figure & Table Captions xii
Chapter 1 Introduction 1
1-1 Background 1
1-2 Characterization of High-k Dielectric Layer 3
1-3 Motivation 6
1-4 Organization of the Thesis 6
Chapter2 The Physical Properties of Thulium Oxide 11
2-1 Introduction 11
2-2 Experiment 11
2-3 Results and Discussion 12
2-3-1 X-ray diffraction (XRD) of Thulium oxide film analysis 12
2-3-2 X-ray photoelectron spectroscopy (XPS) of Thulium oxide film analysis 13
2-3-3 Atomic force microscope (AFM) of thulium oxide film analysis 14
2-4 Summary 14
3-1 Introduction 21
3-2 Experiment 22
3-3 Results and Discussion 22
3-3-1 Capacitor characteristics of Tm2O3 gate dielectric 22
3-3-2 Hysteresis phenomenon and interface state density characteristics of Tm2O3 gate dielectric 23
3-3-3 Comparison of frequency dispersion of Tm2O3 gate dielectric for various temperature 25
3-3-4 J-V characteristics of Tm2O3 gate dielectric 25
3-3-5 Charge trapping characteristics of Tm2O3 gate dielectric 26
3-4 Summary 27
Chapter 4 The Physical Properties of Thulium Titanium Oxide 40
4-1 Introduction 40
4-2 Experiment 40
4-3 Results and Discussion 41
4-3-1 X-ray diffraction (XRD) of thulium titanium oxide film analysis 41
4-3-2 X-ray photoelectron spectroscopy (XPS) of thulium titanium oxide film analysis 41
4-3-3 Atomic force microscope (AFM) of thulium titanium oxide film analysis 43
4-4 Summary 43
5-1 Introduction 49
5-2 Experiment 49
5-3 Results and Discussion 50
5-3-1 Capacitor characteristics of Tm2Ti2O7 gate dielectric 50
5-3-2 Hysteresis phenomenon and interface state density characteristics of Tm2Ti2O3 gate dielectric 51
5-3-3 Comparison of frequency dispersion of Tm2Ti2O7 gate dielectric for various temperature 52
5-3-4 J-V characteristics of Tm2Ti2O7 gate dielectric 53
5-3-5 Charge trapping characteristics of Tm2Ti2O7 gate dielectric 53
5-4 Summary 54
Chapter6 The Physical Properties of Holmium Titanium Oxide 68
6-1 Introduction 68
6-2 Experiment 68
6-3 Results and Discussion 69
6-3-1 X-ray diffraction (XRD) of holmium titanium oxide film analysis 69
6-3-2 X-ray photoelectron spectroscopy (XPS) of holmium titanium oxide film analysis 69
6-3-3 Atomic force microscope (AFM) of holmium titanium oxide film analysis 70
6-4 Summary 71
Chapter 7 The Electrical Properties of Holmium Titanium Oxide 77
7-1 Introduction 77
7-2 Experiment 77
7-3 Results and Discussion 78
7-3-1 Capacitor characteristics of HoTiO3 gate dielectric 78
7-3-2 Hysteresis phenomenon and interface state density characteristics of HoTiO3 gate dielectric 79
7-3-3 Comparison of frequency dispersion of HoTiO3 gate dielectric for various temperature 80
7-3-4 J-V characteristics of HoTiO3 gate dielectric 80
7-3-5 Charge trapping characteristics of HoTiO3 gate dielectric 81
7-4 Summary 81
Chapter8 The Physical Properties of Ytterbium Titanium Oxide 95
8-1 Introduction 95
8-2 Experiment 95
8-3 Results and Discussion 96
8-3-1 X-ray diffraction (XRD) of Ytterbium titanium oxide film analysis 96
8-3-2 X-ray photoelectron spectroscopy (XPS) of ytterbium titanium oxide film analysis 96
8-3-3 Atomic force microscope (AFM) of ytterbium titanium oxide film analysis 98
8-4 Summary 98
9-1 Introduction 105
9-2 Experiment 105
9-3 Results and Discussion 106
9-3-1 Capacitor characteristics of Yb2TiO5 gate dielectric 106
9-3-2 Hysteresis phenomenon and interface state density characteristics of HoTiO3 gate dielectric 107
9-3-3 Comparison of frequency dispersion of Yb2TiO5 gate dielectric for various temperature 108
9-3-4 J-V characteristics of HoTiO3 gate dielectric 109
9-3-5 Charge trapping characteristics of Yb2TiO5 gate dielectric 109
9-4 Summary 110
Chapter 10 Conclusions and Future work 120
10-1 Conclusions 120
10-2 Future work 120
References 120

Figure & Table Captions
Fig. 1- 1 CMOS evolution toward Si nanoelectronics . 9
Fig. 1- 2 Band offset of high-k dielectrics 10
Fig. 2- 1 The process flow of Tm2O3 thin film 17
Fig. 2- 2 XRD of Tm2O3 film after annealing at various temperature in O2 ambient for 30 sec 17
Fig. 2- 3 XPS results of (a) Si 2p, (b) Tm 4d and (c)O 1s in Tm2O3 film after annealing at various temperature 18
Fig. 2- 4 3×3 μm AFM three domain image of Tm2O3 film without PDA 19
Fig. 2- 5 3×3μm AFM three domain image of Tm2O3 film with PDA 600 °C 19
Fig. 2- 6 3×3μm AFM three domain image of Tm2O3 film with PDA 700 °C 20
Fig. 2- 7 3×3μm AFM three domain image of Tm2O3 film with PDA 800 °C 20
Fig. 3- 1 The process flow of Tm2O3 MOS capacitor 30
Fig. 3- 2 The C-V curves for Tm2O3 with different annealed temperatures in O2 ambient for 30s 31
Fig. 3- 3 The CET vs. different annealing temperatures of Tm2O3 gate dielectric 31
Fig. 3- 4 The hysteresis phenomenon of MOS capacitors for as-deposition film and film after annealing at 700 °C 32
Fig. 3- 5 The hysteresis phenomenon of MOS capacitors for different temperature 32
Fig. 3- 6 The interface state density (Dit) of the Tm2O3 gate dielectrics before and after post deposition annealing 33
Fig. 3- 7 C-V frequency dependence of Tm2O3 gate dielectrics with Ar:O2 = 15:10 annealed for (a) as-deposited (b) 600℃, (c) 700℃, (d) 800℃ 35
Fig. 3- 8 The J-V curves for Tm2O3 after different annealed temperatures in O2 ambient 35
Fig. 3- 9 (a) Charge trapping characteristics of Tm2O3 gate film at as-deposited sample. (b) SILC [ΔJ/J(t=0), where ΔJ=J(t)-J(t=0)] vs. stress time for MOS capacitors at as-deposited sample 36
Fig. 3- 10 (a) Charge trapping characteristics of Tm2O3 gate film at 600 oC (b) SILC [ΔJ/J(t=0), where ΔJ=J(t)-J(t=0)] vs. stress time for MOS capacitors at 600 oC 37
Fig. 3- 11(a)Charge trapping characteristics of Tm2O3 gate film at 700 oC (b) SILC [ΔJ/J(t=0), where ΔJ=J(t)-J(t=0)] vs. stress time for MOS capacitors at 700 oC 38
Fig. 3- 12 (a)Charge trapping characteristics of Tm2O3 gate film at 800 oC (b) SILC [ΔJ/J(t=0), where ΔJ=J(t)-J(t=0)] vs. stress time for MOS capacitors at 800 oC 39
Fig. 4- 1 The process flow of Tm2Ti2O7 thin film 45
Fig. 4- 2 The result XRD spectra of Tm2Ti2O7 film after different annealing temperature in O2 ambient 45
Fig. 4- 3 XPS results of (a)Tm 4d, (b) Ti 2p, and (c) O 1s in Tm2Ti2O7 film at various temperature 46
Fig. 4- 4 3×3 μm AFM three domain image of Tm2Ti2O7 film without PDA 47
Fig. 4- 5 3×3μm AFM three domain image of Tm2Ti2O7 film with PDA 600 °C 47
Fig. 4- 6 3×3μm AFM three domain image of Tm2Ti2O7 film with PDA 700 °C 48
Fig. 4- 7 3×3μm AFM three domain image of Tm2Ti2O7 film with PDA 800 °C 48
Fig. 5- 1 The process flow of Tm2Ti2O7 MOS capacitor 57
Fig. 5- 2 The C-V curves for Tm2Ti2O7 with different annealed temperatures in O2 ambient for 30s 58
Fig. 5- 3 The CET with different annealing temperature treatment 58
Fig. 5- 4 The hysteresis phenomenon of MOS capacitors for as-deposition film and film after annealing at 800 °C 59
Fig. 5- 5The hysteresis phenomenon of MOS capacitors for different temperature 59
Fig. 5- 6 The Dit vs. different temperature of Tm2Ti2O7 gate dielectric 60
Fig. 5- 7 C-V frequency dependence of Tm2Ti2O7 gate dielectrics with Ar:O2 = 15:10 annealed for (a) as-deposited (b) 600℃ (c) 700℃ (d) 800℃ 62
Fig. 5- 8 The J-V curves for Tm2Ti2O7 with different annealing temperature 62
Fig. 5- 9 (a) Charge trapping characteristics of Tm2Ti2O7 gate film at as-deposited sample (b) SILC [ΔJ/J(t=0), where ΔJ=J(t)-J(t=0)] vs. stress time for MOS capacitors at as-deposited sample 63
Fig. 5- 10 (a) Charge trapping characteristics of Tm2Ti2O7 gate film at 600 oC sample (b) SILC [ΔJ/J(t=0), where ΔJ=J(t)-J(t=0)] vs. stress time for MOS capacitors at 600 oC sample 64
Fig. 5- 11 (a) Charge trapping characteristics of Tm2Ti2O7 gate film at 700 oC sample (b) SILC [ΔJ/J(t=0), where ΔJ=J(t)-J(t=0)] vs. stress time for MOS capacitors at 700 oC sample 65
Fig. 5- 12 (a) Charge trapping characteristics of Tm2Ti2O7 gate film at 800 oC sample (b) SILC [ΔJ/J(t=0), where ΔJ=J(t)-J(t=0)] vs. stress time for MOS capacitors at 800 oC sample 66
Fig. 6- 1 The process flow of HoTiO3 thin film 73
Fig. 6- 2 XRD of HoTiO3 film after annealing at various temperature in O2 ambient for 30 sec 73
Fig. 6- 3 XPS results of (a) Ho 4d, (b) Ti 2p and (c)O 1s in HoTiO3 film after annealing at various temperature 74
Fig. 6- 4 3×3 μm AFM three domain image of HoTiO3 film without PDA 75
Fig. 6- 5 3×3μm AFM three domain image of HoTiO3 film with PDA 600 °C 75
Fig. 6- 6 3×3μm AFM three domain image of HoTiO3 film with PDA 700 °C 76
Fig. 6- 7 3×3μm AFM three domain image of HoTiO3 film with PDA 800 °C 76
Fig. 7- 1 The process flow of HoTiO3 MOS capacitor 84
Fig. 7- 2 The C-V curves for HoTiO3 with different annealing temperature 85
Fig. 7- 3 The CET vs. different annealing temperatures of HoTiO3 gate dielectric 85
Fig. 7- 4 The hysteresis phenomenon of MOS capacitors for as-deposition film and film after annealing at 800 °C 86
Fig. 7- 5 The hysteresis phenomenon of MOS capacitors with different temperature 86
Fig. 7- 6 The interface state density (Dit) of HoTiO3 gate films as a function of annealing temperature 87
Fig. 7- 7 C-V frequency dependence of HoTiO3 gate dielectrics with Ar : O2 = 15:10 annealed for (a) as-deposited (b) 600℃ (c) 700℃ (d) 800℃ 89
Fig. 7- 8 The J-V curves for HoTiO3 after different annealed temperatures in O2 ambient 89
Fig. 7- 9 (a) Charge trapping characteristics of HoTiO3 gate film at as-deposited sample (b) SILC [ΔJ/J(t=0), where ΔJ=J(t)-J(t=0)] vs. stress time for MOS capacitors at as-deposited sample 90
Fig. 7- 10 (a) Charge trapping characteristics of HoTiO3 gate film at 600 oC (b) SILC [ΔJ/J(t=0), where ΔJ=J(t)-J(t=0)] vs. stress time for MOS capacitors at 600 oC 91
Fig. 7- 11 (a) Charge trapping characteristics of HoTiO3 gate film at 700 oC (b) SILC [ΔJ/J(t=0), where ΔJ=J(t)-J(t=0)] vs. stress time for MOS capacitors at 700 oC 92
Fig. 7- 12 (a) Charge trapping characteristics of HoTiO3 gate film at 800 oC (b) SILC [ΔJ/J(t=0), where ΔJ=J(t)-J(t=0)] vs. stress time for MOS capacitors at 800 oC 93
Fig. 8- 1 The process flow of Yb2TiO5 thin film 101
Fig. 8- 2 XRD of Yb2TiO5 film after annealing at various temperature in O2 ambient for 30 sec 101
Fig. 8- 3 XPS results of (a) Yb 4d, (b) Ti 2p and (c)O 1s in Yb2TiO5 film after annealing at various temperature 102
Fig. 8- 4 3×3 μm AFM three domain image of Yb2TiO5 film without PDA 103
Fig. 8- 5 3×3μm AFM three domain image of Yb2TiO5 film with PDA 600 °C 103
Fig. 8- 6 3×3μm AFM three domain image of Yb2TiO5 film with PDA 700 °C 104
Fig. 8- 7 3×3μm AFM three domain image of Yb2TiO5 film with PDA 700 °C 104
Fig. 9- 1 The process flow of Yb2TiO5 MOS capacitor 112
Fig. 9- 2 The C-V curves for Yb2TiO5 with different annealing temperature 113
Fig. 9- 3 The CET vs. different annealing temperatures of Yb2TiO5 gate dielectric 113
Fig. 9- 4 The hysteresis phenomenon of MOS capacitors for as-deposition film and film after annealing at 800 °C 114
Fig. 9- 5 The hysteresis phenomenon of MOS capacitors with different temperature 114
Fig. 9- 6 The interface state density (Dit) of Yb2TiO5 gate films as a function of annealing temperature 115
Fig. 9- 7 C-V frequency dependence of Yb2TiO5 gate dielectrics with Ar : O2 = 15:10 annealed for (a) as-deposited (b) 600℃ (c) 700℃ (d) 800℃ 117
Fig. 9- 8 The J-V curves for Yb2TiO5 after different annealed temperatures in O2 ambient 117
Fig. 9- 9 (a) Charge trapping characteristics of Yb2TiO5 gate film at as-deposited sample (b) SILC [ΔJ/J(t=0), where ΔJ=J(t)-J(t=0)] vs. stress time for MOS capacitors at as-deposited sample 118
Fig. 9- 10 (a) Charge trapping characteristics of Yb2TiO5 gate film at 600 oC (b) SILC [ΔJ/J(t=0), where ΔJ=J(t)-J(t=0)] vs. stress time for MOS capacitors at 600 oC 119
Fig. 9- 11 (a) Charge trapping characteristics of Yb2TiO5 gate film at 700 oC (b) SILC [ΔJ/J(t=0), where ΔJ=J(t)-J(t=0)] vs. stress time for MOS capacitors at 700 oC 120
Fig. 9- 12 (a) Charge trapping characteristics of Yb2TiO5 gate film at 800 oC (b) SILC [ΔJ/J(t=0), where ΔJ=J(t)-J(t=0)] vs. stress time for MOS capacitors at 800 oC 120
Table 1 This table is extracted from Roadmap。 9
Table 2 Dielectric constant of high-k materials 10
Table 3 The detail process of Tm2O3 thin film 16
Table 4 The detail process of Tm2O3 with various annealing temperature conditions 29
Table 5 The detail process of Tm2Ti2O7 with various deposition time for different annealing temperature 44
Table 6 The detail process of Tm2Ti2O7 with various deposition times for different annealing temperature 56
Table 7 The k-value, capacitance equivalent thickness (CET), hysteresis, and interface state density of Tm2Ti2O7 67
Table 8 The detail process of HoTiO3 thin film 72
Table 9 The detail process of HoTiO3 with various annealing temperature conditions 83
Table 10 The k-value, capacitance equivalent thickness (CET), hysteresis, and interface state density of HoTiO3 94
Table 11 The detail process of Yb2TiO5 thin film 100
Table 12 The detail process of Yb2TiO5 with various annealing temperature conditions 111
Table 13 The k-value, capacitance equivalent thickness (CET), hysteresis, and interface state density of Yb2TiO5 120

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