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研究生:邱志仁
研究生(外文):C. J. Chiu
論文名稱:以無電鍍法成長銅晶種層及其應用於深次微米技術之研究
論文名稱(外文):Study on Electroless-Based Cu Seed Layer for Deep-Submicro Technology and Its Application
指導教授:黃建榮黃建榮引用關係
指導教授(外文):C. J. Huang
學位類別:碩士
校院名稱:南台科技大學
系所名稱:電機工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:英文
論文頁數:117
中文關鍵詞:銅種子層無電鍍金屬化二氧化矽活化
外文關鍵詞:Copper seed layerElectroless plating (ELP)MetallizationSilicon dioxideactivation
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摘要
本論文中,採用無電鍍(Electroless plating)法在低溫環境(30℃)中將銅晶種層(Copper Seed Layer) 成長於Ta/SiO2/Si基板上。此實驗製程中,製備無電鍍銅晶種層前需做基板表面活化處理(activation treatment),活化處理中將Ta/SiO2/Si基板置於PdCl2/HCl水溶液中。活化實驗得知,Ta/SiO2/Si基板在經過7分鐘的活化處理可以得到最佳表面鈀(Pd)含量。無電鍍銅晶種層最佳製備條件為30mM硫酸銅濃度,沉積溫度控制在30℃中,可得到厚度僅50nm的銅晶種層與最佳的表面粗糙度(14nm)。銅晶種層在後續退火中,置於氫氣環境下(250℃),經過60分鐘退火處理後,將使得表面粗糙度降低4nm;並且銅(111)結晶方向在經過熱退火後能有效的增強,以利於電化學鍍銅有較佳的薄膜結構。總而言之,本研究無電鍍晶種層將可應用於內連線金屬化製程。
Abstract
This study presents a process for growing a Cu seed layer on Ta/SiO2/Si substrate using an electroless plating (ELP) process at an extremely low temperature (~30℃). In this process, the activation treatment of Ta/SiO2/Si substrates was carried out by immersion in a PdCl2/HCl solution prior to electroless Cu deposition. The optimum activation time for the substrate was clearly observed to be 7 minutes. The Cu seed layer was uniformly and smoothly deposited in 30 mM CuSO4 concentration for 80 seconds with an average roughness of 14 nm under a thin film 50 nm thick. The grain size of the Cu seed layer was 34 nm. After annealing in hydrogen ambience at 250~350℃, the average roughness of the Cu seed layer was reduced to 4 nm. A proposed mechanism for the ELP of Cu seed layers on Ta/SiO2/Si substrates is also presented.
Contents
English Abstract.……………………………………………….…..v
Chinese Abstract………………….………………………………...vi
誌謝……………………………………………………….vii
Contents.……………………………………………...……….viii
List of Figures.……………………………………………...….xi
List of Table…………………………………..…....…..xiv
第一章 緒 論……………………………………………………………..1
Chapter 1 INTRODUCTION………………………………………..……...3
1.1 Motivation……………………………...……………...……...3
1.2 RC Time Delays…………………………………………………….4
1.3 Electromigration………………………………………………………5
1.4 Material properties…………………………………………...6
第二章 銅沉積的方法……………………………………………………………..8
Chapter 2 DEPOSITION METHODS OF COPPER ……….…………...10
2.1 Physical Vapor Deposition (PVD)……………………………...10
(a) Self Ionized Plasma…………………………………………….10
(b) Long Throw Sputtering (LTS)………………………………….11
2.2 Chemical Vapor Deposition (CVD)………………………………12
2.3 Electroplating Deposition…………………………………………13
2.4 Electroless Deposition…………………………………………….14
2.5 Diffusion Barrier Layer……………………………………………15
2.6 Copper Seed Layer…………………………………………………16
2.7 Dual-damascene………………………………….…………………17
2.8 CMP………………………………………………………………18
第三章 原理和實驗………………………………………………………………20
Chapter 3 PRINCIPLE AND EXPERIMENTAL…………………………………...22
3.1 Activation reaction……………..…………………………………22
3.1.1 Spontaneous reaction……………………………………….22
3.2 Electroless reaction……………………………………..23
3.2.1 Oxidation-Reduction reaction……………………………….24
3.2.2 Adsorption at solid-liquid interface……………………24
3.2.3 Factors influence the rate of a chemical reaction……..26
(a) Temperature affect the rate of a reaction…………………26
(b) Concentration affect the rate of a reaction…………….26
3.3 Experimental……………….……………………………………..27
3.3.1 The activation of Ta/SiO2/Si substrates………………28
3.3.2 Copper Electroless in Acid Copper Electrolyte………28
3.4 Measure…………………………………………………………...29
3.4.1 Sheet Resistance Measurement……………………………..29
3.4.2 Atomic Force Microscopy…………………………………30
3.4.3 Scanning electron microscopy (SEM)………………….…..33
3.4.4 X-Ray Diffraction……………………….…………………..33
第四章 研究和討論……………………………………………………...36
Chapter 4 RESULTS AND DISCUSSION………………………….………38
4.1 Activation of Ta/SiO2/Si substrates…………………….38
4.2 The effect of the CuSO4 concentration………………….39
4.2.1 The atomic force microscopy (AFM) analysis…………….40
4.2.2 The scanning electron microscopy (SEM) analysis…………41
4.2.3 The effect of the average grain size analysis…………..42
4.2.4 The X-ray diffraction (XRD) analysis………………………42
4.2.5 The four-point probe analysis……………………………….43
4.3 The effect of the deposition temperature……………….44
4.3.1 The effect of the average grain size…………………….45
4.3.2 The four-point probe analysis………………………………46
4.3.3 The atomic force microscopy (AFM) analysis………………46
4.3.4 The scanning electron microscopy (SEM) analysis………..46
4.4 Trench filling capability of electroless Cu deposition……….47
4.5 The effect of the annealing in hydrogen ambience…….…..48
4.5.1 The atomic force microscopy (AFM) analysis……………...48
4.5.2 The X-ray diffraction (XRD) analysis………………………49
4.5.3 The scanning electron microscopy (SEM) analysis…………49
第五章 結論與未來工作………………………………………………51
Chapter 5 CONCLUSION AND FUTURE WORKS……………………………..52
5.1 Conclusions……………………………………………………….52
5.2 Future Works………………………………………………………53
Reference………………………………………………………………….54
Publication…………………………………………………………..103
作者簡介…………………………………………………………103
List of Figures
Figure 1.1 Comparision of intrinsic gare delay and interconnection delay (RC) as a function of the feature size, adopted from Jeng et al……………………60
Figure 1.2 Schematic diagram of an interconnect system, where P is the metal pitch, W the metal width, S the space between metals, T the metal thickness CLL the lateral line to line capacitance, Cv the vertical layer-to-layer capacitance, and CLG line-to-group capacitance…………………………61
Figure 1.3 Show the electromigration process……………...………………………..62
Figure 1.4 The benefits of using Cu and/or low-k dielectrics are illustrated………...63
Figure 2.1 Process step for the fabrication of a via and line level by the dual-demascene approach (adapted from Reference): (a) Insulator deposition; (b) via definition; (c) line definition; (b) barrier and seed layer deposition; (e) plating and CMP…………………………………………64
Figure 2.2 Schematic of a CMP system……………………………………………65
Figure 2.3 Schematic of a linear polishing system…………………………………..66
Figure 3.1 Schematic Gibbs free energy diagram……………………………………67
Figure 3.2. Scheme of the reaction mechanism for Electroless Cu………………….68
Figure 3.3. Illustration of a solid-liquid interface: (a) in the liquid, the molecular distribution is approximately uniform, although some molecules may be adsorbed to produce a small surface excess (black circles); (b) for a solution of surface-active solute (black ovals) extensive adsorption will occur, producing a significant interfacial region of excess solute concentration……………………………………………………………..69
Figure 3.4 Schematic diagram of fabricated structure……………………………….70
Figure 3.5 Schematic diagram of the apparatus for Electroless Cu seed layer………71
Figure 3.6 Experimental step………………………………………………………..72
Figure 3.7 Schematic illustration of an atomic force microscope…………………..73
Figure 3.8 The effect of crystal size on diffraction…………………………………..74
Figure 3.9 Effect of fine particle size on diffraction curves………………………..75
Figure 4.1 The surface element of PdCl2 activation process was observed by EDX at activation room temperature……………………………………………76
Figure 4.2 SEM micrographs of palladium (Pd) activation Ta barrier layer with various activation time (a) 0 min, (b) 1 min, (c) 3 min, (d) 5 min, (e) 7 min, (f) 9 min at room temperature……………………………………………77
Figure 4.3 The Cu film thickness versus deposition time with CuSO4 concentration as a parameter for deposition time 80 seconds at deposition temperature 30℃…………………………………………………………………………78
Figure 4.4 shows the variation of the deposition rate for electroless Cu seed layer is dependent on different CuSO4 concentration at 30℃………………….79
Figure 4.5 The variation in the roughness of electroless Cu seed layer with different deposition time at deposition temperature 30℃……………………….80
Figure 4.6 The AFM surface micrographs of 30mM CuSO4 concentration in deposition time 80 seconds at 30℃………………...………………….81
Figure 4.7 The AFM surface micrographs of 40mM CuSO4 concentration in deposition time 80 seconds at 30℃…………………………………..82
Figure 4.8 The AFM surface micrographs of 50mM CuSO4 concentration in deposition time 80 seconds at 30℃……………………………………83
Figure 4.9 The SEM in different CuSO4 concentration: (a) 30 mM; (b) 40 mM; and (c) 50 mM for deposition time 80 seconds at deposition temperature 30℃.………………………………………………………………………84
Figure 4.10 (a) 20mM, (b) 30mM, (c) 40mM, at deposition temperature 30℃ for deposition time 80 seconds……………………………………………85
Figure 4.11 shows the variation of the average grain size for electroless Cu seed layer is dependent on different CuSO4 concentration at 30℃………………86
Figure 4.12 XRD pattern for the Cu seed layer/Ta/SiO2/Si structures is dependent on different CuSO4 concentration for deposition time 80 second at 30℃....87
Figure 4.13 shows the variation of the resistivity for electroless Cu seed films is dependent on different CuSO4 concentration at 30℃…………………..88
Figure 4.14 The Cu film thickness versus deposition time with deposition temperature as a parameter for 30mM CuSO4 concentration……………………….89
Figure 4.15 shows the variation of the deposition rate for electroless Cu seed layer is dependent on different deposition temperature in 30mM CuSO4 concentration………………………………………………..…………90
Figure 4.16 The Cu film grain size versus deposition time with deposition temperature as a parameter for 30mM CuSO4 concentration…………………………………………………………91
Figure 4.17 The Cu film resistivity versus deposition time with deposition temperature as a parameter for 30mM CuSO4 concentration……….92
Figure 4.18 The Cu film average roughness versus deposition time with deposition temperature as a parameter for 30mM CuSO4 concentration………..93
Figure 4.19 (a) 70s, (b) 80s, (c) 90s, in 30mM CuSO4 concentration at deposition temperature 30℃…………………………………………………...….94
Figure 4.20 A SEM cross-sectional view of the Cu seed layer on Ta/SiO2/Si with a film thickness of 50 nm at a deposition temperature of 30℃ for a deposition time of 80 seconds…………………………………..……..95
Figure 4.21 Shows also the effect of the different activation time is trench fill ability…………………………………………………………………..96
Figure 4.22 The dependence of average roughness on annealing time at different annealing temperatures for a deposition time of 80 seconds in a 30 mM CuSO4 concentration at 30℃. The annealing processes were performed in hydrogen ambience………………………………………………..97
Figure 4.23 XRD pattern for the Cu seed layer/Ta/SiO2/Si structures; (a) as-deposited and after annealing at (b) 150℃, (c) 250℃, (d) 350℃ for 60 minutes in H2 ambience………………………………………………………….98
Figure 4.24 SEM pattern for the Cu seed layer/Ta/SiO2/Si structures; (a) as-deposited and after annealing at (b) 150℃, (c) 250℃, (d) 350℃ for 60 minutes in H2 ambien……………………………………………………………99
List of Tables
Table 1.1. Comparison of material properties…….………………………….……100
Table 3.1 Solution composition for Pd activation process………………..……….101
Table 3.2 The experimental of additives in typically standard electrolyte…………102
REFERENCE
[1] J. R. Lloyd, J. J. Ciement, “Electromigration in copper conductors”, Thin Solid Films, 262, (1995) p. 135.
[2] T. Nguyen, L. J. Charneski, D. R. Evans, “Temperature Dependence of the Morphology of Copper Sputter Deposited on TiN Coated Substrates”, J. Electrochem. Soc., 144, (1997) p. 3634.
[3] Christian Wenzel, Norbert Urbansky, Wolfgang Klimes, Peter Siemroth, Thomas Schulke, “Gap fill with PVD processes for copper metallized integrated circuits”, Microelectron. Eng., 33, (1997) p. 31.
[4] Stephan Riedel, Jurgen Rober, “Electrical properties of copper films produced by MOCVD”, Microelectron. Eng., 33, (1997) p. 165.
[5] Sung Kwan Kwak, Kwan Soo Chung, Ikmo park, H. Lim, Curre., “Substrate and pretreatment dependence of Cu nucleation by metal-organic chemical vapor deposition”, Appl. Phys., 2, (2002) p. 205.
[6] Kyeong-Keun Choi, Shi-Woo Rhee, “Chemical vapor deposition of copper film from HexafluoroacetylacetonateCu(I)vinylcyclohexane”, Thin Solid Films, 397, (2001) p. 70.
[7] Yi-Mao Lin, Shi-Chern Yen, “Effects of additives and chelating agents on electroless copper plating”, Appl. Sur. Sci., 178, (2001) p. 116.
[8] Seok Woo Hong, Chang-Hee Shin, and Jong-Wan Park, “Palladium Activation on TaNx Barrier Films for Autocatalytic Electroless Copper Deposition”, J. Electrochem. Soc., 149, (2002) p. G85.
[9] J. H. Lin, Y. Y. Tsai, S. Y. Chiu, T. L. Lee, C. M. Tsai, P. H. Chen, C. C. Lin, M. S. Feng, C. S. Kou, H. C. Shih, “Palladium seeding on the tantalum-insulated silicon oxide film by plasma immersion ion implantation for the growth of electroless Copper”, Thin Solid Films, 377-378, (2000) p. 592.
[10] C. J. Huang and C. J. Chiu, Improved of Surface Roughness and Sheet Resistance in the Metal-Semiconductor (M-S) Junction by Electroless Plating (ELP) Process, submitted to J. Electrochem. Soc. Dec. 2002.
[11] Naik, M.B., Gill, W.N., Wentorf, R.H., and Reeves, R.R., “CVD of Copper by using Copper (I) and Copper (II) b-Diketonates”, Thin Solid films, 262, (1995) p. 60.
[12] J. Torres, “Advanced Copper Interconnections for Silicon CMOS Technologies”, Appl. Surf. Sci., 91, (1995) p. 112.
[13] Hong Jie Jin, Masaharu Shiratani, Takashi Kawasaki, Tsuyoshi Fukuzawa, Toshio Kinoshita, and Yukio Watanabe, “Plasma-enhanced metal organic chemical vapor deposition of high purity copper thin films using plasma reactor with the H atom source”, J. Vac. Sci. Technol., A 17(3), (1999) p. 726.
[14] V. M. Dubin, Y. Shacham-Diamandad, B. Zhao, P. K. Vasudev, C. H. Ting, “Electroless Copper Deposition for Ultralarge Scale Integration”, J. Electrochem. Soc., 144(3), (1997) p. 898.
[15] P. C. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkans, H. Deligianni, “Damascene copper electroplating for chip interconnection”, IBM J. Res. Develop., 42, (1998) p. 567.
[16] S. P. Jeng, R. H. Havemann, and M. C. Chang, Mater. Res. Soc. Symp. Proc., 337, (1994) p. 25.
[17] Hong Xiao, “Introduction to Semiconductor Manufacturing technology”, Chap. 11, Prentice Hall, New York , p. 453 (2001).
[18] Shyam P. Murarka, Materials Science and Engineering, R19, (1997) p. 87.
[19] Y. S. Diamand, V. Dubin and M. Angyal, “Electroless Copper Deposition for ULSI”, Thin Solid Films, 262, (1995) p. 93.
[20] Y. S. Diamand, and V. Dubin, “Copper Electroless Deposition Technology for Ultra-Large-Scale-Integration (ULSI) Metallization”, Microelectroic Engineering, 33, (1997) p. 47.
[21] N. Bourhila, J. Torres, J. Palleau, C. Bernard, R. Madar, “Copper LPCVD for advanced technology”, Microelectron. Eng., 33, (1997) p. 25.
[22] Stephan Riedel, Jurgen Rober, Thomas Geβner, “Electrical properties of copper films produced by MOCVD”, Microelectron. Eng., 33, (1997) p. 165.
[23] D. Davazoglou, S. Vidal and A. Gleizes, “ Elective chemical vapor deposition of copper on AZ 5214TM-patterned licon substrates”, J. Vac. Sci. Technol., B19(3), (2001) p. 759.
[24] Hong Jie Jin, Masaharu Shiratani, Takashi Kawasaki, Tsuyoshi Fukuzawa, Toshio Kinoshita, and Yukio Watanabe, ” Plasma-enhanced metal organic chemical vapor deposition of high purity copper thin films using plasma reactor with the H atom source”, J. Vac. Sci. Technol., A17(3), (1999) p. 726.
[25] Junhwan Oh, Jaegab Lee, Chongmu Lee, “ Plasma pretreatment of the Cu seed layer surface in Cu electroplating”, Mater. Chem. and Phy., 73, (2002) p. 227.
[26] Anette A. Rasmussen, Jens A. D. Jensen, Andy Horsewell, Marcel A. J. Somers, “ Microstructure in electrodeposited copper layer; the role of the substrate”, Electrochimica Acta, 47, (2001) p. 67.
[27] Elias D. Eliadis, Ralph G. Nuzzo, Andrew A. Gewirth, and Richard C. Alkire, ” Copper Deposition in the Presence of Surface-Confined Additives”, J. Electrochem. Soc., 144, (1997) p. 96.
[28] T. P. Moffat, J. E. Bonevich, W. H. Huber, A. Stanishevsky, D. R. Kelly, G. R. Stafford, and D. Josell, “Superconformal Electrodeposition of Copper in 500-90 nm Features”, J. Electrochem. Soc., 147, (2000) p. 4524.
[29] K. Kondo, J. lshikawa, O. Takenaka, and T. Matsubara, “ Acceleration of Electroless Copper Deposition in the presence of Excess Triethanolamine”, J. Electrochem. Soc., 138, (1991) p. 3629.
[30] Yosi Shacham-Diamand, Sergey Lopatin, “ Integrated electroless metallization for ULSI”, Electrochimica Acta, 44, (1999) p. 3639.
[31] Tohru Hara, Yuichi Yoshida, and Hiroki Toida, “ Improved Barrier and Adhesion Properties in Sputtered TaSiN Layer for Copper Interconnections”, Electrochemical and Solid-State Letters, 5, (2002) p. G36.
[32] T. Yamauchi and T. Yamaoka, K. Yashiro, S. Sobue, “Effect of internal stresses and microstructure of sputtered TiN films on solid-phase reactions with Al-Si-Cu alloy films”, J. Appl. Phys., 78, (1995). p. 2385
[33] Tomi Laurila, Kejun Zeng, and Jorma K. Kivilahti “ Failure mechanism of Ta diffusion barrier between Cu and Si”, J. Appl. Phys., 88, (2000) p. 3377.
[34] P. C. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkans, H. Deligianni, “ Damascene copper electroplating for chip interconnections”, IBM J. Res. Develop., 42, (1998) p. 567.
[35] M. M. Chow, J. E. Cronin, W. L. Guthrie, W. Kaanta, B. Luther, W. J. Patrick, K. A. Perry, and C. L. Standley, "Method for Producing Coplanar Multi-Level Metal/Insulator Films on a Substrate and for Forming Patterned Conductive Lines Simultaneously with Stud Vias," U.S. Patent 4,789,648, December 6, 1988.
[36] C.-K. Hu and J. M. E. Harper, "Copper Interconnections and Reliability," Mater. Chem. Phys., 52, (1998) p. 5.
[37] Hong Xiao, “Introduction to Semiconductor Manufacturing technology”, Chap. 10, Prentice Hall, New York, p. 518 (2001).
[38] Hong Xiao, “Introduction to Semiconductor Manufacturing technology”, Chap. 10, Prentice Hall, New York, p. 518 (2001).
[39] Seok Woo Hong, Chang-Hee Shin, and Jong-Wan Park, “ Palladium Activation on TaNx Barrier Films for Autocatalytic Electroless Copper Deposition”, J. Electrochem. Soc., 149, (2002) p. G85.
[40] J. H. Lin, Y. Y. Tsai, S. Y. Chiu, T. L. Lee, C. M. Tsai, P. H. Chen, C. C. Lin, M. S. Feng, C. S. Kou, H. C. Shih, “Pd seeding on the Ta-insulated silicon oxide film by PIII for the growth of electroless Cu”, Thin Solid Films, 377-378, (2000) p. 592.
[41] J Philip Bromberg, “PHYSICAL CHEMISTRY”, Boston (1980) p. 315.
[42] Drew Myers, “SURFACES, INTERFACES, AND COLLOIDS”, Chap. 9, VCH Publishers, Inc. (1991).
[43] Thomas Tayler, et al., Solid state Technology, 47 (1998).
[44] M. Paunovic, Plating, 55 (1968) p. 1161.
[45] Dieter K. Schroder “Semiconductor material and device characterization”, p. 713 (1998).
[46] D. Sarid, Scanning Force Microscopy with Applications to electric, Magnetic, and atomic forces, Oxford University Press , New York, 1991.
[47] Q Zhong, D. Inniss, K. Kjoller, and V. B. Elings, “Fractured Polymer/ Silica Fiber Surface Studied by Tapping Mode Atomic Force Microscopy,” Surf. Sci. Lett. 290, L668-L692, 1993.
[48] B. D. CULLITY, “ELEMENTS OF X-RAY DIFFRACTION”, Addison-wesley publishing company, Inc., Ch3, pp. 99-102 and Ch9, pp. 284-285(1978).
[49] Dieter K. Schroder, “semiconductor material and device characterization”, Wiley-Interscience Pubilcation, ch10, pp.704-708(1998).
[50] J. Philip Bromberg, Physical Chemistry, Electrochemical cells, Allyn and Bacon, Inc., Boston (1980) pp. 311-338.
[51] B. D. Cullity, “Elements of X-ray Diffraction”, Addison-Wesley Publishing Company, Inc., California (1959) p. 99.
[52] Hong Hui Hsu, Ching Wei Teng, and Jien Wei Yeh, J. Electrochem. Soc., 149, (2002) p. C143.
[53] Hong Xiao, “Introduction to Semiconductor Manufacturing technology”, Prentice Hall, New York p. 381 (2001).
[54] G. Oskam, J. G. Long, A Natarajan and P C Searson, J. Phys. D: Appl. Phys., 31, (1998) p. 1927.
[55] Kyeong Keun Choi and Shi Woo Rhee, Effect of Carrier Gas on Chemical Vapor Deposition of Copper with (Hexafluoroacetylacetonate) Cu(I) (3,3-Dimethyl-1-butene), J. Electrochem. Soc. 148 (2001) p. C473.
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