臺灣博碩士論文加值系統

近年來許多研究專注於管線式類比數位轉換器的數位校正，在此篇論文裡介紹一個增益誤差校正技術，可利用低增益放大器來製作高解析的類比數位轉換器，此技術利用校正電容陣列來調整回授因子，因此回授增益也跟著做校正來減少增益誤差。在此電路設計中，我們使用39.1dB放大增益的放大器來實現十位元的管線式類比數位轉換器，此前景式校正技術只需要192個轉換時脈即可完成校正。
根據量測結果，本晶片在40MHz的轉換頻率下的DNL和INL分別為+0.77/-0.55LSB和+1.45/-1.03LSB，在輸入頻率為20MHz且工作在80MHz的轉換頻率下時，量測到的SNDR和SFDR分別為54.97dB和63.96dB，把輸入頻率提高到40MHz且工作在320MHz的轉換頻率時，其SNDR和SFDR分別為53.43dB和61.8dB，操作在1.2伏特電壓時功率消耗為47.2mW，全部的晶片面積大小為0.93mm2，然而主動電路所占的面積只有0.21mm2。

The pipelined ADCs with the digital calibrations have been researched in recently years. In this thesis, a gain-error self-calibration technique is presented to allow low-gain operation amplifiers (opamps) to use in high-precision pipelined ADCs. The proposed technique reduces gain error by using a calibration capacitor array. It adjusts the feedback factor; therefore, the closed-loop gain is calibrated. In the circuit design, 39.1dB open-loop gain opamps can be used for a 10-bit pipelined ADC. Only 192 clock cycles are required for the proposed foreground self-calibration technique.
According to the measurement results, the prototype ADC exhibits a DNL of +0.77/-0.55LSB and an INL of +1.45/-1.03LSB at the sampling rate of 40MS/s. With 20MHz input frequency, the SNDR and SFDR achieve 54.97dB and 63.96dB at 80MS/s. The SNDR and SFDR are 53.43dB and 61.8dB at 320MS/s with 40MHz input. The power consumption is 47.2mW at 1.2V supply. The active area is 0.21mm2 and whole chip with pads occupies 0.93mm2.

致謝 I
摘要 II
Abstract III
Table of Contents IV
List of Figures VIII
List of Tables XII
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
Chapter 2 Fundamentals of Analog-to-Digital Converter 5
2.1 Introduction 5
2.2 Performance Metrics 5
2.2.1 Offset and Gain Error 5
2.2.2 Differential and Integral Nonlinearity (DNL, INL)5
2.2.3 Signal-to-Noise Ratio (SNR) 7
2.2.4 Total Harmonic Distortion (THD) 8
2.2.5 Spurious-Free Dynamic Range (SFDR) 8
2.2.6 Signal-to-Noise and Distortion Ratio (SNDR) 9
2.2.7 Effective Number of Bits (ENOB) 9
2.2.8 Figure of Merit (FoM) 10
2.3 Architecture of Analog-to-Digital Converters 10
2.3.1 Flash ADC 10
2.3.2 Two-Step ADC 12
2.3.4 Folding ADC 13
2.3.5 Pipelined ADC 15
2.3.4 Successive-Approximation ADC 16
2.4 Summary 18
Chapter 3 A Gain-Error Self-Calibration Technique 19
3.1 Introduction 19
3.2 Propose MDAC Architecture 20
3.3 Analysis on Calibration Capacitor Array 23
3.4 The Gain-Error Self-Calibration Procedure 26
3.5 Opamp Offset Cancellation 30
3.6 Summary 32
Chapter 4 Circuit Implementation and Simulation Resul 33
4.1 Introduction 33
4.2 Circuit Implementation 34
4.2.1 MDAC 34
4.2.2 Opamp 36
4.2.3 Bias and CMFB Circuit 37
4.2.4 Comparator 39
4.2.5 Bootstrap Circuit 41
4.2.6 Clock Generator 43
4.3 Simulation Results 44
4.3.1 Opamp Simulation 44
4.3.1.1 AC Analysis 44
4.3.1.2 DC Analysis 46
4.3.2 MDAC Transient Analysis 46
4.3.3 DNL and INL Simulation 50
4.3.4 FFT Simulation 51
4.4 Summary 53
Chapter 5 Test Setup and Measurement Results 55
5.1 Introduction 55
5.4 Floor Plan and Layout Considerations 55
5.2 Test Setup 57
5.3 PCB Design 58
5.5 Experiment Results 62
5.5.1 Static Performance 65
5.5.2 Dynamic Performance 67
5.6 Summary 70
Chapter 6 Conclusions 73
Bibliography 75

[1]B.Razavi, Principles of Data Conversion System Design. Wiley-IEEE Press, 1995.
[2]Rudy van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters. Kluwer Academic Publishers, 2003.
[3]D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997.
[4]P. R. Gray, et al., Analysis and Design of Analog Integrated Circuits. New-York: Wiley, 2001.
[5]S-C. Lee, K.-D. Kim, J.-K. Kwon, et al., “A 10-bit 400-MS/s 160-mW 0.13-μm CMOS dual-channel pipeline ADC without channel mismatch calibration,” IEEE J. Solid-State Circuits, vol. 41, pp. 1596-1605, Jul. 2006.
[6]B. R. Gregoire and U.-K. Moon, “An over-60 dB true rail-to-rail performance using correlated level shifting and an opamp with 30 dB loop gain,” in ISSCC Dig. Tech. Papers, Feb. 2008, pp. 540–541.
[7]B. Murmann and B. E. Boser, “A 12 b 75 MS/s pipelined ADC using open-loop residue amplification,” in ISSCC Dig. Tech. Papers, Feb. 2003, pp. 328–329.
[8]Y. Chiu, C. W. Tsang, B. Nikolic, and P. R. Gray, “Least mean square adaptive digital background calibration of pipelined analog-to-digital converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, pp. 38–46, Jan. 2004.
[9]J. McNeill, M. Coln, and B. Larivee, “A Split-ADC architecture for deterministic digital background calibration of a 16b 1 MS/s ADC,” in ISSCC Dig. Tech. Papers, Feb. 2005, pp. 276–598.
[10]B. Razavi and B. A. Wooley, “Design Techniques for High-Speed, High- Resolution Comparators,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916-1926, Dec. 1992.
[11]Y. M. Lin, B. Kim, and P. R. Gray, “A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS,” IEEE J. Solid-State Circuits, vol. 26, pp. 628-636, Apr. 1991.
[12]H. W. Chen, I. C. Chen, H. C. Tseng, and H. S. Chen, “A 1-GS/s 6-bit Two- Channel Two-Step ADC in 0.13-μm CMOS,” IEEE J. Solid-State Circuits, vol. 44, pp. 3051-3059, Nov. 2009.
[13]Limotyrakis, S.; Kulchycki, S.D.; Su, D.K.; Wooley, B.A., “A 150-MS/s 8-b 71- mW CMOS time-interleaved ADC,” IEEE J. Solid-State Circuits, vol. 40, pp. 1057-3059, May. 2005.
[14]Byung-Moo Min; Kim, P.; Bowman, F.W., III; Boisvert, D.M.; Aude, A.J., “A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC,” IEEE J. Solid-State Circuits, vol. 38, pp. 2031-2039, Dec. 2003.
[15]Abo, A.M.; Gray, P.R., “A 1.5-V 10-bit 14.3-MS/s CMOS pipeline analog-to- digital converter,” IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, May. 1999.
[16]Jong-Bum Park, Sang-Min Yoo, Se-Won Kim, Young-Jae Cho, Seung-Hoon Lee, “A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth,” IEEE J. Solid-State Circuits, vol. 39, Issue 8, Aug. 2004.
[17]Kang-Wei Hsueh, Yu-Kai Chou, Yu-Hsuan Tu, Yi-Fu Chen, Ya-Lun Yang, Hung-Sung Li, “A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2008, pp. 546–634.
[18]Seung-Chul Lee; Young-Deuk Jeon; Kwi-Dong Kim; Jong-Kee Kwon; Jongdae Kim; Jeong-Woong Moon; Wooyol Lee, “A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications,” in ISSCC Dig. Tech. Papers, Feb. 2007, pp. 458–615.
[19]Y. Chiu, P. R. Gray and B. Nikolic, “A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR,” IEEE J. Solid-State Circuits, vol. 39, pp. 2139–2151, Dec. 2004.