臺灣博碩士論文加值系統

本論文分析電感電容壓控振盪器的物理結構關係，結合振盪理論，建構滿足設計規格的設計窗口；並透過Mathematica軟體建立具最佳化之自動化電感電容壓控振盪器設計程式。首先，考量半導體製程的變異，自動化設計程式加入製程變異造成設計窗口的縮減程度，掌握電路特性偏移量，已可大幅提高電路設計的準確性；同時，透過設計窗口與模型參數關連分析，在製程技術及電路架構不變的情況下，自動化設計程式所獲得的設計點已具最佳化之效能。最後，搭配ADS模擬驗證及實際晶片製作，成功驗證本設計程式之準確性及可行性。透過與ADS軟體驗證其可應用範圍，證實本自動化設計程式可運用的範圍已完整包含目前通訊上常用的頻段範圍(1 GHz~10.6 GHz)。且透過本設計程式在設計時間上只需花費16秒即可達成自動化及最佳化設計，並符合未來單晶片射頻積體電路系統快速設計的需求。

This thesis proposes a design window technology to establish an automatic program on p-n cross-couple LC voltage controlled oscillator (LC-VCO). By considering the variation on semiconductor fabrications, the circuit accuracy has been improves greatly through the program. The optimal property design points are derived at the same time through analyzing the design window and the modeling parameters. Since good agreements were derived by comparing the results with the ADS circuit simulator and the measured data on the test chips, accuracy and feasibility of the program were verified. Furthermore, it is also demonstrated that the program is applicable for the applications on the commonly used frequency range for the communication system (1 GHz ~10.6 GHz), and only 16 seconds of computation time is needed to reach an optimization design. Consequently, it is concluded that the program is able to greatly assist the RFIC design in the future.

誌謝 ii
摘要 iii
ABSTRACT iv
目錄 v
表目錄 viii
圖目錄 x
1. 緒論 1
1.1 前言 1
1.2 文獻回顧 3
1.3 研究目的 5
1.4 論文架構 6
2. 理論 7
2.1 振盪理論 7
2.1.1 巴克豪森準則 7
2.1.2 負電阻理論 8
2.2 設計窗口 9
2.2.1 振盪器結構考量 9
2.2.2 設計參數縮減 12
2.2.3 可調頻率範圍限制 13
2.2.4 工作電壓限制 15
2.2.5 啟動條件限制 17
2.2.6 設計窗口 19
2.3 振盪器特性指標 20
2.3.1 相位雜訊 20
2.3.2 可調頻率範圍 27
2.3.3 功率損耗 28
3. 實驗規劃 30
3.1 電路架構與主被動元件 31
3.1.1 電路架構 31
3.1.2 主動元件 32
3.1.3 螺旋電感 33
3.1.4 可變電容 33
3.2 自動化電路設計流程 34
3.2.1 建立自動化設計程式 37
3.2.2 製程變異 37
3.2.3 伴隨製程變異的設計窗口調變 40
3.2.4 建立電路特性指標的關係式 41
3.2.5 最佳化設計點的評判 45
3.3 電感電容壓控振盪器晶片製作流程 46
3.3.1 製作流程 46
3.3.2 佈局考量 47
3.3.3 佈局後模擬 48
3.4 量測規劃 51
4. 結果與討論 54
4.1 自動化電路設計與特性指標分析 54
4.1.1 設計窗口與模型參數關聯分析 67
4.1.2 最佳化設計分析 71
4.1.3 自動化設計程式限制條件 72
4.2 電感電容壓控振盪器設計驗證 74
4.2.1 功率損耗分析 75
4.3晶片製作 76
4.3.1 設計點選擇與電路特性模擬 77
4.3.2 環境變異模擬 83
4.3.3 相關文獻比較 88
4.4 量測結果 90
4.5 改進方法及應用範圍 97
5. 結論 100
參考文獻 102
附錄A 電感元件模型參數萃取方法 108
附錄B 可變電容元件模型參數萃取方法 112
自傳 115

[1]ITRS,“Design,” International Technology Roadmap for Semiconductors 2005 Edition, 2005.
[2]ITRS,“Radio Frequency and Analog/Mixed-Signal Technologies for Wireless Communications,” International Technology Roadmap for Semiconductors 2005 Edition, 2005.
[3]Svelto, F., Deantoni, S., and Castello, R., “A 1.3GHz Low-Phase Noise Fully Tunable CMOS LC VCO,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 3, pp. 356–361, Mar. 2000.
[4]Straayer, M., Cabanillas, J., and Rebeiz, G. M., “A Low-Noise Transformer-Based 1.7 GHz CMOS VCO,” IEEE/ISSCC, Texas, USA, pp. 286–287, Feb. 2002.
[5]Lin, T. Y., Juang, Y. Z., Wang, H. Y., and Chiu, C. F., “A Low Power 2.2-2.6 GHz CMOS VCO with a Symmetrical Spiral Inductor,” IEEE/ISCAS International Conference, Bangkok, Thailand, Vol. 1, pp. 641-644, May 2003.
[6]Tu, H. L., Yang, T. Y., and Chiou, H. K., “Low Phase Noise VCO Design with Symmetrical Inductor in CMOS 0.35-m Technology,” IEEE Microwave Conference, Yokohama, Japan, Dec. 2005.
[7]Sia, C. B., Yeo, K. S., Goh, W. L., Swe, T. N., Ng, C. Y., Chew, K. W., Loh, W. B., Chu, S., and Chan, L., “Effects of Polysilicon Shield on Spiral Inductors for Silicon-Based RF IC’s,” IEEE/VLSI Technology Systems and Applications, Hsinchu, Taiwan, pp. 158–161, Apr. 2001.
[8]Tiemeijer, L. F., Havens, R. J., Pavlovic, N., and Leenaerts, D. M. W., “Record Q Symmetrical Inductors for 10-GHz LC-VCOs in 0.18 m Gate-Length CMOS,” IEEE Electron Devices Letters, Vol. 23, No. 12, pp. 713–715, Dec. 2002.
[9]Yim, S. M., Chen, T., and O, K. K., “The Effect of a Ground Shield on the Characteristics and Performance of Spiral Inductors,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 2, pp. 237–244, Feb. 2002.
[10]Tiemeijer, L. F., Havens, R. J., Bouttement, Y., and Pranger H. J., “Physics-Based Wideband Predictive Compact Model for Inductors With High Amounts of Dummy Metal Fill,” IEEE Transactions on Microwave theory and Techniques, Vol. 54, No. 8, pp. 3378–3386, Aug. 2006.
[11]Cheung, T. S. D. and Long, J. R., “Shielded Passive Devices for Silicon-Based Monolithic Microwave and Millimeter-Wave Integrated Circuits,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 5, pp. 1183–1200, May 2006.
[12]Wu, C. H., Kuo, C. Y., and Liu, S. I., “Selective Metal Parallel Shunting Inductor and Its VCO Application,” IEEE Transactions on Circuits and Systems, Vol. 52, No. 9, pp. 1811-1818, Sep. 2005.
[13]Li, T. L., Huang, S., Hung, B., Tzeng, C. Y., Liang, V., and Chien, S. C., “Design of High-Q MIS-Varactor with Layout Modification,” Solid State Devices and Materials Conference, Tsukuba, Japan, pp. 400–401, Sep. 2008.
[14]Morandini, Y., Larchanche, J. F., and Gaquiere, C., “High Frequency Characterization of Compact N+Poly/Nwell Varactor Using Waffle-Layout,” IEEE/SiRF, Orlando, USA, pp. 167–170, Jan. 2008.
[15]Hegazi, E., Sjoland, H., and Abidi, A. A., “A Filtering Technique to Lower LC Oscillator Phase Noise,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 12, pp. 1921–1930, Dec. 2001.
[16]Andreani, P. and Sjoland, H., “A 2.2 GHz CMOS VCO with Inductive Degeneration Noise Suppression,” IEEE/CICC, California, USA, pp. 197–200, May 2001.
[17]Choi, J., Kim, H., and Kim, B., “A Low Phase Noise 2 GHz VCO Using 0.13 m CMOS Process,” IEEE Microwave Conference, Yokohama, Japan, Dec. 2005.
[18]Qi, H. and Yuhao, Z., “A 2.4 GHz CMOS VCO Design,” IEEE International Conference on Microelectronics, Tokyo, Japan, pp. 98–101, Dec. 2007.
[19]Shin, Y., Kim, T., Kim, S., Jang, S., and Kim, B., “A Low Phase Noise Fully Integrated CMOS LC VCO Using a Large Gate Length pMOS Current Source and Bias Filtering Technique for 5-GHz WLAN,” IEEE/ISSSE, Montreal, Canada, pp. 521–524, Aug. 2007.
[20]Wang, H., Wu, N., and Shou, G., “A Novel CMOS Low-Phase Noise VCO with Enlarged Tuning Range,” IEEE/ICMMT, Nanjing, China, pp. 570–573, Apr. 2008.
[21]Hsieh, H. H. and Lu, L. H., “A Low-Phase-Noise K-Band CMOS VCO,” IEEE Microwave and Wireless Components Letters, Vol. 16, No. 10, pp. 552–554, Oct. 2006.
[22]Berny, A. D., Niknejad, A. M., and Meyer, R. G., “A Wideband Low-Phase-Noise CMOS VCO,” IEEE/CICC, California, USA, pp. 555–558, Sep. 2003.
[23]Fard, A., “Phase Noise and Amplitude Issues of a Wide-Band VCO Utilizing a Switched Tuning Resonator,” IEEE/ISCAS, Kobe, Japan, pp. 2691–2694, May 2005.
[24]Wu, C. Y. and Yu, C. Y., “A 0.8 V 5.9 GHz Wide Tuning Range CMOS VCO Using Inversion-Mode Bandswitching Varactors,” IEEE/ISCAS, Kobe, Japan, pp. 5079–5082, May 2005.
[25]Broussev, S. S., Lehtonen, T. A., and Tchamov, T. N., “A Wideband Low Phase-Noise LC-VCO With Programmable Kvco,” IEEE Microwave and Wireless Components Letters, Vol. 17, No. 4, pp. 274–274, Apr. 2007.
[26]Park, D. and Cho, S., “A Power-Optimized CMOS LC VCO with Wide Tuning Range in 0.5-V Supply,” IEEE/ISCAS, Kobe, Japan, pp. 3233–3236, Apr. 2006.
[27]Kurachi, S., Yoshimasu, T., Itoh, N., and Yonemura, K., “5-GHz Band Highly Linear VCO IC with a Novel Resonant Circuit,” IEEE/SiRF, California, USA, pp. 285–288, Jan. 2007.
[28]Hershenson, M., Hajimiri, A., Mohan, S. S., Boyd, S. P., and Lee, T. H., “Design and Optimization of LC Oscillators,” IEEE/ACM International Conference, San Francisco, USA, pp. 65-69, Nov. 1999.
[29]Issa, D. B., Kachouri, A., and Samet, M., “Concepts and Optimization of CMOS LC VCO Circuits via Geometric Program,” IEEE/DTIS International Conference, Singapore, pp. 1-6, Mar. 2008.
[30]Razavi, B., Design of Analog CMOS Integrated Circuits, McGraw-Hill, Los Angeles, USA, 2001.
[31]張辰嘉， “最佳化電感電容壓控振盪器設計方法之研究” ，國防大學中正理工學院碩士學位論文，桃園，第7-26頁，2008年。
[32]劉深淵、楊清淵，鎖相迴路，滄海書局，台中，第62-102頁，2006年。
[33]Ham, D. and Hajimiri, A., “Concepts and Methods in Optimization of Integrated LC VCOs,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 6, pp. 896-909, June 2001.
[34]Andreani, P. and Mattisson, S., “On the Use of MOS Varactors in RF VCO’s,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 6, pp. 905-910, June 2000.
[35]鄧德生， “單晶無線通訊射頻積體電路技術研究” ，國防大學中正理工學院博士學位論文，桃園，2006年。
[36]Razavi, B., RF Microelectronics, Prentice Hall PTR, Los Angeles, USA, pp. 50-52, 1998.
[37]葉景祥， “以最佳化電感品質因子提升壓控振盪器效能之研究” ，國防大學中正理工學院碩士學位論文，桃園，2007年。
[38]Hajimiri, A. and Lee, T. H., “A general Theory of Phase Noise in Electrical Oscillators,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 2, pp. 179-194, Feb. 1998.
[39]Lee, T. H., The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, California, USA, 1998.
[40]Tiebout, M., Low Power VCO Design in CMOS, Springer, Munich, Germany, pp. 5-9, 2005.
[41]Jerng, A. and Sodini, C. G., “The Impact of Device Type and Sizing on Phase Noise Mechanisms,” IEEE/CICC, San Jose, USA, pp. 547–550, Sep. 2003.
[42]Fard, A. and Andreani, P., “An Analysis of 1/f2 Phase Noise in Bipolar Colpitts Oscillators (With a Digression on Bipolar Differential-Pair LC Oscillators),” IEEE Journal of Solid-State Circuits, Vol. 42, No. 2, pp. 374–384, Feb. 2007.
[43]Dellsperger, T., Kromer, C., and Sialm, G., Design of a 5 GHz VCO in CMOS, ETH, Zurich, Switzerland, pp. 11-30, 2002.
[44]Srirattana, N., Heo, D., Park, H. M., Raghavan, A., Allen, P. E., and Laskar, J., “A New Analytical Scalable Substrate Network Model for RF MOSFETs,” IEEE MTT-S Digest, Texas, USA, pp. 699-702, June 2004.
[45]Chen, T. S., Lee, C. Y., and Kao, C. H., “An Efficient Noise Isolation Technique for SOC Application,” IEEE Transactions on Electron Devices, Vol. 51, No. 2, pp. 255-260, Feb. 2004.
[46]Bunch, R. L. and Reman, S., “Large-Signal Analysis of MOS Varactors in CMOS -Gm LC VCOs,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 8, pp. 1325-1332, Aug. 2003.
[47]施敏、梅凱瑞原著，林鴻志譯，半導體製程概論，國立交通大學出版社，新竹，第271-332頁，2005年。
[48]Jenei, S., Nauwelaers, B. K. J. C., and Decoutere, S., “Physics-Based Closed-Form Inductance Expression for Compact Modeling of Integrated Spiral Inductors,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 1, pp. 77-80, Jan. 2002.
[49]高世平， “可調節的射頻金氧半場效電晶體模型之研究” ，國防大學中正理工學院碩士學位論文，桃園，第52-99頁，2008年。
[50]Hajimiri, A. and Lee, T. H., “Design Issues in CMOS Differential LC Oscillators,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, pp. 717–724, May 1999.
[51]Amselem, E., Gonzalez, B., Garcia, J., Aldea, I., Marrero, M., Iturri, A. G., Pino, J. D., Khemchandani, S. L., and Hernandez, A., “Influence of Gate Geometry in Integrated MOS Varactors on Accumulation Mode for RF,” IEEE/CDE, Spanish, pp. 68–70, Feb. 2007.
[52]Crols, J., Kinget, P., Craninckx, J., and Steyaert, M., “An Analytical Model of Planar Inductors on Lowly Doped Silicon Substrates for High Frequency Analog Design up to 3 GHz,” IEEE/VLSI Circuits Digest of Technical, San Francisco, USA, pp. 28–29, June 1996.
[53]Maget, J., Tiebout, M., and Kraus, R., “MOS Varactors With n- and p-Type Gates and Their Influence on an LC-VCO in Digital CMOS,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 7, pp. 1139-1147, July 2003.