臺灣博碩士論文加值系統

在這論文中，我們設計一個合成器來合成各種組合電路，建立以開關電晶體為主的元件庫，元件庫包含了四種型態的元件，且每種元件提供四種驅動力以供合成器選擇，輸入為乘積總合的布林函數的格式，可以同時輸入數個函數讓硬體共享，並且提供各種模式給使用者選擇，主要有高效能、高密度，以針對速度和面積來做最佳化，並且提供合成動態電路，最後會輸出Verilog gate-level code、HSPICE netlist，以提供Verilog-in和模擬使用。元件庫的元件數量少，所需建立的佈局圖就比較少，即使製程下降，我們也可以快速將資訊重新建立，輕易地轉移到更低的製程。

In this thesis, A pass-transistor-based cell library containing four types of cells is designed and the corresponding logic/circuit synthesizer is developed for logic mapping of any combinational and dynamic circuits. There are four driven capability selects for each type of cells. The format of input is Boolean functions with expressions of sum of product and we can input several functions for hardware sharing at the same time. It provides several optional modes such as high density、high performance、dynamic logic circuit, etc. . It also does optimization for both area and speed performance. The final, output is Verilog gate-level code and HSPICE netlist that provide Verilog-in for automatic place-and-route and simulation. Due to the small number of cells in library, it is easy to migrate to a new process technology.

第１章 導論 1
１.１ 動機 1
１.２ 前置作業 3
１.３ 相關工作 4
第２章 BDD的產生 7
２.１ 簡介 7
２.２ 使用者界面 8
２.３ 合成器流程 9
２.４ 資料結構 11
２.４.１ 變數表 12
２.４.２ 子函數共享 14
２.５ 測試樣本產生 16
第３章 速度、面積、功率的考量 18
３.１ 簡介 18
３.２ 反相器加入 18
３.３ 四選一多工器 29
３.４ 切割 31
３.５ 推動力選擇 33
３.６ DOMINO-LIKE邏輯電路 34
３.７ DOMINO電路 36
第４章 合成器實作 37
４.１ 簡介 37
４.２ 反相器的選定 37
４.３ 元件庫 39
４.４ 推動力選擇 40
４.５ DOMINO-LIKE 邏輯電路 43
４.６ DOMINO電路 45
４.７ TIMING ESTIMATE 46
第５章 合成器多種模式的效能比較 48
５.１ 簡介 48
５.２ 反向器加入的比較 49
５.３ 四選一多工器 50
５.４ 切割效能比較 51
５.５ 推動力選擇效能比較 51
５.６ DOMINO與DOMINO-LIKE 電路比較 52
５.７ 各種模式面積和速度比較 53
第６章 結論與未來展望 59
６.１ 結論 59
６.２ 未來展望 59
參考文獻 60

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